Abstract: A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the second pillar regions being provided in paired state and alternately, in a device portion and a terminal portion surrounding the device portion, along a surface on the side of a second electrode disposed on the opposite side of the first semiconductor region from the first electrode. The semiconductor device further includes a lateral RESURF (reduced surface field) region of the second conductivity type disposed at a surface portion, on the opposite side from the first semiconductor region, of the second semiconductor region in the terminal portion.

Abstract: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

Abstract: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

Abstract: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

Abstract: A semiconductor device includes: a first semiconductor region of a first conductivity type disposed on the side of a first electrode; and a second semiconductor region having first pillar regions of the first conductivity type and second pillar regions of a second conductivity type, the first pillar regions and the second pillar regions being provided in paired state and alternately, in a device portion and a terminal portion surrounding the device portion, along a surface on the side of a second electrode disposed on the opposite side of the first semiconductor region from the first electrode. The semiconductor device further includes a lateral RESURF (reduced surface field) region of the second conductivity type disposed at a surface portion, on the opposite side from the first semiconductor region, of the second semiconductor region in the terminal portion.

Abstract: Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region.

Abstract: A resistor (45) of semiconductor material is formed on an insulating layer (42), then a silicon nitride film (46) is deposited on the entire surface including the resistor (45), and a silicon dioxide film (47) is sequentially deposited thereon, and thereafter electrodes (49A) and (49B)of the resistor (45) are formed, thereby preventing the fragility of the insulating layer (51) at step portions of the resistor (45), preventing the breakage of the electrodes and interconnections, and improving a withstand voltage between the resistor (45) and the interconnections crossing over it to thereby improve yield of a semiconductor device.

Abstract: A semiconductor device fabricating method removes bird's head formed in the edges of a SiO.sub.2 film formed by a recessed LOCOS process in fabricating a semiconductor device. The semiconductor device fabricating method comprises steps of forming device isolating regions (6) on a silicon substrate (1) by a recessed LOCOS process, forming an insulating film (10) over the entire surface of the work, and simultaneously forming contacts of a polycrystalline silicon film (15) between the device isolating regions (6) and resistors of the polycrystalline silicon film (15) over the device isolating regions (6). Portions of the polycrystalline silicon film (15) corresponding to the bird's heads in the edges of the insulating film (10) are removed selectively, and exposed portions of the insulating film (10) and the bird's heads in the device isolating regions (6) are removed sequentially by etching to flatten the surface of the work.

Abstract: In a semiconductor device, a first diffusion region on a surface of an output region for a substrate electric potential, and an element segregation third diffusion region under a field insulating layer, are electrically connected together through a second diffusion region. Thus, the substrate electric potential can be easily output at the surface of the output region, even if the first diffusion region on the surface of the output region is formed shallow by a fabrication process at low temperature due to fine designing of the semiconductor device. A patterning process of the output region in the form of a protruded shape is also required, but the process is completed through a procedure using only one ion implantation and one low temperature thermal oxidation, thereby dramatically simplifying the fabrication process.

Abstract: A method for the manufacture of a semiconductor device, comprising the steps of forming ohmic contact portions at the same time, then forming a semiconductor layer on the entire surface including the open portions, and selectively introducing impurities by ion implantation into the contact portions of the semiconductor layer and isolated other element regions, thereby producing a transistor and other elements. This method results in the simultaneous production of a transistor and other elements and simplifies the steps of the process of manufacture.

Abstract: In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device.