Patents by Inventor Hiroki Ikeda

Hiroki Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system handling a plurality of bits as a unit to be processed
    Patent number: 4561072
    Abstract: An addressing system for a memory circuit which reads out plural locations simultaneously and then arranges the readout information into a desired sequence or format.
    Type: Grant
    Filed: October 21, 1983
    Date of Patent: December 24, 1985
    Assignee: NEC Corporation
    Inventors: Takeshi Arakawa, Hiroki Ikeda
  • Memory system handling a plurality of bits as a unit to be processed
    Patent number: 4434502
    Abstract: A memory system for simultaneously extracting a desired block of data in response to an address specifying only the center bit of the block. The input address is modified through an arithmetic circuit wherein the address representing the center bit is added to and subtracted from to produce a plurality of addresses which are used to address a plurality of separate memory blocks. The outputs from the memory blocks are passed through a selection alignment matrix circuit which selects from the outputs of the memory blocks only those bits in the desired block of data and aligns those bits in a predetermined array. Bits other than those in the desired block of data are discarded.
    Type: Grant
    Filed: April 3, 1981
    Date of Patent: February 28, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Takeshi Arakawa, Hiroki Ikeda