Abstract: The wafer test system includes: a prober including a chuck that holds a semiconductor wafer and a probe card having probe needles thereon, and brings the probe needles in contact with semiconductor chips formed on the semiconductor wafer to inspect the semiconductor chips; an overhead hoist transport that delivers the cassette that houses the plurality of semiconductor wafers to be inspected to the prober and withdraws, from the prober, the cassette that houses the semiconductor wafers that have been inspected; a conveying control unit that controls the overhead hoist transport to convey the probe card between a replacement position of the probe card predetermined in the prober and a storage of the probe card located in a place different from the prober; and a card conveying mechanism that conveys the probe card between a holding position in the prober and the replacement position.

Abstract: Provided is a communication device that operates as a management node in a first zone being a management domain on a network, the communication device including a communication unit that executes communication with another node and a control unit that controls communication executed by the communication unit. The control unit operates such that, when having received, from a user, a request regarding an application that chains one or more application functions (AFs) to act on a packet flowing in the network, the control unit acquires information regarding the application from a second zone being a management domain other than the first zone, and then calculates a deployment destination of the AFs in the network including the first zone and the second zone based on the information.

Abstract: An information processing apparatus operates as an IoTSP 1 (corresponding to an example of “first IoTSP”) that provides a service for causing a user to acquire sensor data. The information processing apparatus includes a communication unit that executes communication with another IoTSP (corresponding to an example of “second IoTSP other than the first IoTSP”) and a control unit that searches the sensor data corresponding to an acquisition request of the user via an application and responds to the user with the searched sensor data. The control unit searches the sensor data from the other IoTSP via the communication unit based on an identifier of the other IoTSP included in the acquisition request and policy information indicating propriety of information sharing between the IoTSPs and uses a protocol interface including the same procedure as a procedure between the application and IoTSP1 when searching the sensor data.

Abstract: There is provided a method of producing a polymerizable composition that includes a first polymerizable monomer; and a second polymerizable monomer, a polymer of the second polymerizable monomer, or both, the second polymerizable monomer, the polymer of the second polymerizable monomer, or the both being dispersed in the first polymerizable monomer, the method of producing a polymerizable composition includes dissolving the first polymerizable monomer; the second polymerizable monomer, the polymer of the second polymerizable monomer, or the both in a solvent to obtain a solution in a first step; and evaporating the solvent from the solution in a second step, wherein the first polymerizable monomer is a liquid, and wherein the second polymerizable monomer is a solid.

Abstract: Provided is a fixing rotating member capable of maintaining high toner releasability over longer periods of time than in conventional instances and that is capable of maintaining abrasion resistance against paper; the fixing rotating member comprises a base layer, an elastic layer, and a surface layer, in this order; the surface layer containing a tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer and a perfluoropolyether; the tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer having pores formed therein; the surface layer has pores with openings at a first surface thereof, and constituting an outer surface of the fixing rotating member; at least part of the pores containing the perfluoropolyether; a content of the perfluoropolyether in the surface layer is 20 mass % to 60 mass %; and a degree of orientation A of molecules of the tetrafluoroethylene-perfluoroalkyl vinyl ether in a direction perpendicular to a circumferential direction of the surface layer is 35 to 75%.

Abstract: A fixing rotating member comprising a base layer, an elastic layer and a surface layer, in this order, the surface layer containing PFA and PFPE, and having pores with openings at a first surface; at least part of the pores containing the PFPE, wherein when after removing the PFPE in the pores, placing a first observation region on the first surface, defining a ratio of a sum of areas of the openings in the first observation region relative to an area of the first observation region as P1; and placing a second observation region in a cross section of the surface layer, and defining a ratio of a sum of areas of the pores in the second observation region relative to an area of the second observation region as P2, P2/P1 is 1.3 or higher.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface on one side thereof and a second surface on an opposite side thereof, and having an element therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at the one side of the first surface of the first semiconductor layer, an insulating layer disposed on the first surface of the first semiconductor layer, and a charge-attracting layer configured to attract electrical charges generated in the insulating layer when a predetermined voltage is supplied to the charge-attracting layer.

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract: A semiconductor device including a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface on one side thereof and a second surface on an opposite side thereof, and having an element therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at the one side of the first surface of the first semiconductor layer, an insulating layer disposed on the first surface of the first semiconductor layer, and a charge-attracting layer configured to attract electrical charges generated in the insulating layer when a predetermined voltage is supplied to the charge-attracting layer.

Abstract: A semiconductor device including a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.

Abstract: A semiconductor device includes an SOI substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and an interlayer insulation film formed on the SOI substrate. The SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region. The circuit layer includes a plurality of single pixel circuits arranged in an array pattern. The single pixel circuit includes a circuit element, a diode, and a conductive portion. The diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region. The conductive portion is electrically isolated from other elements. The conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface on an opposite side thereof, and having a sensor therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at said one side of the primary surface of the first semiconductor layer, an insulating layer formed between the first semiconductor layer and the second semiconductor layer, and being disposed on the primary surface of the first semiconductor layer, and a charge-attracting semiconductor layer of the first conductivity type configured to attract electrical charges generated in the insulating layer when a fixed voltage is supplied to the charge-attracting semiconductor layer.

Abstract: A semiconductor device including: a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract: A semiconductor device includes an SOI substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and an interlayer insulation film formed on the SOI substrate. The SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region. The circuit layer includes a plurality of single pixel circuits arranged in an array pattern. The single pixel circuit includes a circuit element, a diode, and a conductive portion. The diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region. The conductive portion is electrically isolated from other elements. The conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film.

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract: A semiconductor device includes a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member. The first penetrating electrode is electrically connected only to the first semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface on an opposite side thereof, and having a sensor therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at said one side of the primary surface of the first semiconductor layer, an insulating layer formed between the first semiconductor layer and the second semiconductor layer, and being disposed on the primary surface of the first semiconductor layer, and a charge-attracting semiconductor layer of the first conductivity type configured to attract electrical charges generated in the insulating layer when a fixed voltage is supplied to the charge-attracting semiconductor layer.

Abstract: The present disclosure provides a semiconductor device including: a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.