Patents by Inventor Hiroki Kimura
Hiroki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9306578Abstract: An oscillator includes an oscillator circuit, a crystal filter, a package portion, and a heating portion. The oscillator circuit is configured to output an oscillation signal. The crystal filter has a frequency characteristic where an attenuation at a detuned frequency is larger than an attenuation at an oscillation frequency of the oscillation signal. The detuned frequency is a frequency different from the oscillation frequency. The package portion covers a crystal blank of the oscillator circuit and a crystal blank of the crystal filter. The heating portion is configured to heat the crystal blank of the oscillator circuit and the crystal blank of the crystal filter using a resistor disposed between: a wiring board to which the package portion is secured, and the package portion.Type: GrantFiled: December 16, 2014Date of Patent: April 5, 2016Assignee: NIHON DEMPA KOGYO CO., LTD.Inventors: Hiroki Kimura, Naoki Onishi
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Patent number: 9293578Abstract: Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film.Type: GrantFiled: July 3, 2013Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Publication number: 20150171872Abstract: An oscillator includes an oscillator circuit, a crystal filter, a package portion, and a heating portion. The oscillator circuit is configured to output an oscillation signal. The crystal filter has a frequency characteristic where an attenuation at a detuned frequency is larger than an attenuation at an oscillation frequency of the oscillation signal. The detuned frequency is a frequency different from the oscillation frequency. The package portion covers a crystal blank of the oscillator circuit and a crystal blank of the crystal filter. The heating portion is configured to heat the crystal blank of the oscillator circuit and the crystal blank of the crystal filter using a resistor disposed between: a wiring board to which the package portion is secured, and the package portion.Type: ApplicationFiled: December 16, 2014Publication date: June 18, 2015Inventors: HIROKI KIMURA, NAOKI ONISHI
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Publication number: 20150041883Abstract: An object of the present invention is to improve the ESD resistance of an electrostatic protection element. The essence of the basic idea resides in that an electrostatic protection element ESD is configured to include not a thyristor or an npn bipolar transistor, but a pnp bipolar transistor so as to be connected in parallel with a diode. In other words, the essence of the basic idea resides in that an electrostatic protection element ESD is constituted by a diode parasitically provided with a pnp bipolar transistor.Type: ApplicationFiled: August 6, 2014Publication date: February 12, 2015Inventors: Hiroki Kimura, Youhei Yanagida, Kenji Miyakoshi, Tomoyuki Miyoshi, Takayuki Ooshima
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Publication number: 20140284714Abstract: Disclosed is a semiconductor device that includes a first MOS transistor having a predetermined size and a second MOS transistor having a lager size than the first MOS transistor. The first MOS transistor is divided into two or more sections, each paired with a corresponding section of the second MOS transistor to form a unit cell. As the unit cell is cyclically formed on a substrate, the current mirror ratio between the total size of the first MOS transistor and the total size of the second MOS transistor remains unaffected by the nonuniformity of position-dependent temperature distribution.Type: ApplicationFiled: February 27, 2014Publication date: September 25, 2014Inventors: Kenji Miyakoshi, Youhei Yanagida, Hiroki Kimura, Takayuki Ooshima
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Patent number: 8771410Abstract: An ink composition for ballpoint pens comprises a coloring agent, a liquid medium, a polyoxyethylene castor oil and/or a polyoxyethylene hardened castor oil, or a derivative thereof, and one compound or a mixture of two or more compounds selected from the group consisting of a monoalkyl ether phosphoric acid, a polyoxyethylene monoalkyl ether phosphoric acid, a dialkyl ether phosphoric acid, a polyoxyethylene dialkyl ether phosphoric acid, a trialkyl ether phosphoric acid, and a polyoxyethylene trialkyl ether phosphoric acid.Type: GrantFiled: January 22, 2010Date of Patent: July 8, 2014Assignee: Pentel Kabushiki KaishaInventors: Aya Otsubo, Ikuo Takagishi, Kiyonori Yasuike, Hiroki Kimura, Takashi Sekine
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Patent number: 8655584Abstract: A map data utilization apparatus retrieves a version information of map data for a specific area when a current position of a vehicle is updated. Then, the version information of the map data of the specific area is compared with a version information of the map data of an identical area in a version list that is retrieved in advance for map data updating. When the version of the map data in the version list is different from the one of the map data of the specific area, an inquiry screen is displayed on a display unit for inquiring a user whether the map data is updated. When an update is instructed by the user, map data update data is acquired from an information center, and the map data of the specific area is updated by using the map data update data.Type: GrantFiled: September 28, 2007Date of Patent: February 18, 2014Assignee: DENSO CORPORATIONInventor: Hiroki Kimura
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Publication number: 20140015049Abstract: An LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, and feeding regions of the first and second conduction types formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region is formed at a distance from the field oxide film in an end portion in a longitudinal direction, and desirably the feeding region is intermittently formed at given intervals in the longitudinal direction, and the feeding region is applied to the first semiconductor region.Type: ApplicationFiled: July 3, 2013Publication date: January 16, 2014Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
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Patent number: 8446192Abstract: A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit 3 provides a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS circuit 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.Type: GrantFiled: June 11, 2010Date of Patent: May 21, 2013Assignee: Nihon Dempa Kogyo Co., LtdInventor: Hiroki Kimura
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Patent number: 8232808Abstract: There is provided a switch circuit for switching whether to output an input signal, including: a transmission path that transmits the input signal from an input end to an output end of the switch circuit; a first semiconductor switch that is provided on the transmission path and switches whether to transmit the input signal; a second semiconductor switch that is opened when the first semiconductor switch is short-circuited, and that is short-circuited when the first semiconductor switch is opened, thereby grounding, to a ground potential, a high-frequency signal leaked to the transmission path between the first semiconductor switch and the output end; and a voltage controller that causes a potential difference on both ends of the second semiconductor switch when the second semiconductor switch is opened.Type: GrantFiled: September 10, 2008Date of Patent: July 31, 2012Assignee: Advantest CorporationInventors: Hiroki Kimura, Chisato Maeda
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Patent number: 8125255Abstract: Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.Type: GrantFiled: February 22, 2011Date of Patent: February 28, 2012Assignee: Nihon Dempa Kogyo Co., LtdInventors: Hiroki Kimura, Naoki Onishi, Shoichi Tsuchiya
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Patent number: 8115527Abstract: There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator according to whether the amplitude level falls within the proper range or not.Type: GrantFiled: February 10, 2011Date of Patent: February 14, 2012Assignee: Nihon Dempa Kogyo Co., Ltd.Inventor: Hiroki Kimura
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Publication number: 20110271870Abstract: A ballpoint pen ink ensuring a very soft and smooth writing feel even when a strong writing pressure is applied, is obtained. A ballpoint pen ink containing a colorant, a liquid medium, a polyoxyethylene castor oil and/or a polyoxyethylene hardened castor oil, or a derivative thereof, and one kind or a mixture of two or more kinds selected from a monoalkyl ether phosphoric acid, a polyoxyethylene monoalkyl ether phosphoric acid, a dialkyl ether phosphoric acid, a polyoxyethylene dialkyl ether phosphoric acid, a trialkyl ether phosphoric acid, a polyoxyethylene trialkyl ether phosphoric acid and their neutralization products or solutions.Type: ApplicationFiled: January 22, 2010Publication date: November 10, 2011Applicant: Pentel Kabushiki KaishaInventors: Aya Otsubo, Ikuo Takagishi, Kiyonori Yasuike, Hiroki Kimura, Takashi Sekine
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Patent number: 8044722Abstract: To provide a highly stable oscillation frequency control circuit wherein the frequency thereof is corrected, an adequate range of the input levels of external reference signals is determined in accordance with temperature characteristics in detecting the external reference signal, and the control voltage to a VCO is controlled within and outside the adequate range. An oscillation frequency control circuit includes a selection switch that connects the phase comparator to the loop filter in an external reference synchronization mode and that connects the fixed voltage supplying circuit to the loop filter in a fixed voltage mode, and a CPU that switches the selection switch to the external reference synchronization mode or to the fixed voltage mode based on whether the detected voltage of an external reference signal level is within or outside of the adequate range.Type: GrantFiled: November 12, 2009Date of Patent: October 25, 2011Assignee: Nihon Dempa Kogyo Co., LtdInventor: Hiroki Kimura
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Publication number: 20110221490Abstract: There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator according to whether the amplitude level falls within the proper range or not.Type: ApplicationFiled: February 10, 2011Publication date: September 15, 2011Applicant: NIHON DEMPA KOGYO CO., LTD.Inventor: Hiroki Kimura
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Publication number: 20110204935Abstract: Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.Type: ApplicationFiled: February 22, 2011Publication date: August 25, 2011Inventors: Hiroki Kimura, Naoki Onishi, Shoichi Tsuchiya
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Patent number: 7893774Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: GrantFiled: June 29, 2010Date of Patent: February 22, 2011Assignee: Nihon Dempa Kogyo Co., LtdInventors: Yasuo Kitayama, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Publication number: 20100315137Abstract: A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit 3 provides a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS circuit 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.Type: ApplicationFiled: June 11, 2010Publication date: December 16, 2010Inventor: Hiroki Kimura
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Patent number: 7821344Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: GrantFiled: July 22, 2008Date of Patent: October 26, 2010Assignee: Nihon Dempa Kogyo Co., LtdInventors: Yasuo Kitayama, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Publication number: 20100264962Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Inventors: Yasuo KITAYAMA, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto