Abstract: A semiconductor integrated circuit includes a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point, and a second register configured to store and retain the first value, and not to update the first value to the second value.

Abstract: An object of the present invention is to solve a problem that, if the state of a macro that is a debug target changes by a factor other than a debugger while the debugger debugs the macro as a target, the debugger becomes unable to continue debugging and the debugging terminates abnormally. In order to solve the aforementioned problem, disclosed is a semiconductor integrated circuit including a first register that stores a value indicating that the macro is in a reset state in response to a reset signal received during debugging of the macro, and a second register that stores a value indicating whether or not the macro has been in the reset state in the past by receiving a reset signal.

Abstract: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m?2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Abstract: Disclosed is a memory controller which is disposed between a CPU and a memory, receives from the CPU a control signal (TRANS) indicating whether a type of a bus cycle is a sequential cycle in which an address continuous with an address of an immediately preceding bus cycle is output to the memory as an address of a current bus cycle or a nonsequential cycle in which an address unrestricted by the address of the immediately preceding bus cycle is output to the memory as an address of a current bus cycle. The memory controller outputs a control signal (RDY) for notifying completion of the bus cycle to the CPU. In this memory controller, an address assuming the sequential cycle is generated in advance from the current address before completion of the bus cycle. Then, the address assuming the sequential cycle is supplied to the memory in a next cycle. Read data from the memory corresponding to the address assuming the sequential cycle is then output to the CPU.

Abstract: An object of the present invention is to solve a problem that, if the state of a macro that is a debug target changes by a factor other than a debugger while the debugger debugs the macro as a target, the debugger becomes unable to continue debugging and the debugging terminates abnormally. In order to solve the aforementioned problem, disclosed is a semiconductor integrated circuit including a first register that stores a value indicating that the macro is in a reset state in response to a reset signal received during debugging of the macro, and a second register that stores a value indicating whether or not the macro has been in the reset state in the past by receiving a reset signal.

Abstract: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m?2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Abstract: A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between flip-flops included in the scan chain, a first bypass path bypassing the first macro cell, a first selection circuit selecting the first macro cell or the first bypass path, a second macro cell placed in a path between flip-flops included in the scan chain, a second bypass path bypassing the second macro cell, and a second selection circuit selecting the second macro cell or the second bypass path. The first selection circuit and the second selection circuit operate individually.

Abstract: Disclosed is a memory controller which is disposed between a CPU and a memory, receives from the CPU a control signal (TRANS) indicating whether a type of a bus cycle is a sequential cycle in which an address continuous with an address of an immediately preceding bus cycle is output to the memory as an address of a current bus cycle or a nonsequential cycle in which an address unrestricted by the address of the immediately preceding bus cycle is output to the memory as an address of a current bus cycle. The memory controller outputs a control signal (RDY) for notifying completion of the bus cycle to the CPU. In this memory controller, an address assuming the sequential cycle is generated in advance from the current address before completion of the bus cycle. Then, the address assuming the sequential cycle is supplied to the memory in a next cycle. Read data from the memory corresponding to the address assuming the sequential cycle is then output to the CPU.

Abstract: A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises a tag memory 1 for storing an address tag of an address of a cache data and a first valid bit for showing the presence of validity of the cache data in a set of blocks in response to an index, and a valid bit register 2 for storing a second valid bit corresponding to the first valid bit, and resetting the second valid bit, and the valid bit is generated based on the first valid bit and the second valid bit.

Abstract: A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between flip-flops included in the scan chain, a first bypass path bypassing the first macro cell, a first selection circuit selecting the first macro cell or the first bypass path, a second macro cell placed in a path between flip-flops included in the scan chain, a second bypass path bypassing the second macro cell, and a second selection circuit selecting the second macro cell or the second bypass path. The first selection circuit and the second selection circuit operate individually.

Abstract: A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises a tag memory 1 for storing an address tag of an address of a cache data and a first valid bit for showing the presence of validity of the cache data in a set of blocks in response to an index, and a valid bit register 2 for storing a second valid bit corresponding to the first valid bit, and resetting the second valid bit, and the valid bit is generated based on the first valid bit and the second valid bit.