Patents by Inventor Hiroki Miyake
Hiroki Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125635Abstract: To enable accurate measurement of a flow rate of a gas flowing in a non-metallic tube. An ultrasonic flowmeter includes a first wedge member having a first angle, a second wedge member having a second angle, and a flow rate measurement unit that measures a flow rate of a gas based on a propagation time difference of a longitudinal wave excited by a tube. The first angle and the second angle are configured such that the tube excites both a longitudinal wave and a shear wave, and a mixing ratio of the shear wave to the longitudinal wave is 10% or less.Type: ApplicationFiled: September 24, 2023Publication date: April 18, 2024Applicant: Keyence CorporationInventors: Hiroki MATSUI, Daiki MATSUMOTO, Ryuma MIYAKE
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Publication number: 20240129962Abstract: A base station apparatus, configured to establish a wireless link for a backhaul line with a relay apparatus, and provide a first period in which a radio resource is used by the base station apparatus for the backhaul line, and a second period in which the radio resource is not used by the backhaul line.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: KDDI CORPORATIONInventors: Hiroki TAKEDA, Xiao SHAO, Yasutomo MIYAKE, Shingo WATANABE
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Patent number: 11953461Abstract: An electrode formed by molding a semiconductor device with resin. The electrode comprises: a first resin mold portion formed on a front surface of the semiconductor device and having a first thickness (t1); a second resin mold portion formed on a back surface of the semiconductor device and having a second thickness (t2) greater than the first thickness; and an exposed portion formed in a part of the first resin mold portion corresponding to an end of the semiconductor device.Type: GrantFiled: April 8, 2019Date of Patent: April 9, 2024Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Ukyo Ikeda, Tetsuyoshi Ono, Hiroki Nakatsuchi, Masafumi Miyake
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Publication number: 20240021681Abstract: A semiconductor device includes a semiconductor substrate having an element region and a peripheral region. The semiconductor substrate includes a high-concentration layer, a drift layer, and a low-concentration layer. The high-concentration layer extends from the element region to the peripheral region, and is in contact with a lower electrode. The high-concentration layer has a thin plate portion and a thick plate portion. The drift layer is in contact with the upper surface of the thick plate portion. The low-concentration layer extends from the element region to the peripheral region, and is in contact with an upper surface of the thin plate portion and a side surface of a stepped portion at a boundary between the thin plate portion and the thick plate portion. A half or more of a quadrilateral region in a cross section of the semiconductor substrate is not depleted.Type: ApplicationFiled: July 12, 2023Publication date: January 18, 2024Inventors: TATSUJI NAGAOKA, HIROKI MIYAKE
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Patent number: 11862477Abstract: A method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting.Type: GrantFiled: December 15, 2021Date of Patent: January 2, 2024Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies CorporationInventors: Shuhei Ichikawa, Hiroki Miyake
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Publication number: 20230369417Abstract: A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventor: Hiroki MIYAKE
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Publication number: 20230359487Abstract: A control device includes a processor, a storage, and a scheduler. The storage includes a first program for real time control processing of the control target, the first program having a highest priority of execution executed by the processor in the period, a second program for related processing related to real time control, the second program having a lower priority of execution than that of the first program, and a third program of a system service, the third program having a lower priority of execution than that of the second program and being executed when a spare time of the processor exists in the period. The scheduler interrupts the execution of the second program to start the execution of the third program when the execution of the second program is started and then when a predetermined type of an instruction code is executed in the second program within the period.Type: ApplicationFiled: December 17, 2020Publication date: November 9, 2023Applicant: OMRON CORPORATIONInventors: Masahiko NAKANO, Hiroki MIYAKE, Takafumi OKURA, Masanori OTA, Tetsushi JAKUNEN
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Patent number: 11757009Abstract: A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.Type: GrantFiled: August 10, 2021Date of Patent: September 12, 2023Assignees: DENSO CORPORATION, MIRISE Technologies Corporation, TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Hiroki Miyake
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Patent number: 11699600Abstract: A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.Type: GrantFiled: November 9, 2021Date of Patent: July 11, 2023Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation, National University Corporation Kyoto Institute of TechnologyInventors: Tatsuji Nagaoka, Hiroki Miyake, Hiroyuki Nishinaka, Yuki Kajita, Masahiro Yoshimoto
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Publication number: 20230081110Abstract: In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H2SO4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.Type: ApplicationFiled: August 18, 2022Publication date: March 16, 2023Inventors: KATSUHIRO KUTSUKI, KEITA KATAOKA, DAIGO KIKUTA, HIROKI MIYAKE, SHUHEI ICHIKAWA, YOSHITAKA NAGASATO
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Publication number: 20220246474Abstract: A method for manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate; and dividing the substrate at a position including a current region where the electric current is caused to flow and along a cleavage plane of the substrate. A method for manufacturing a semiconductor device includes: stacking a first substrate and a second substrate each made of the compound semiconductor; and bonding the first substrate and the second substrate by causing an electric current to flow between the first substrate and the second substrate.Type: ApplicationFiled: January 25, 2022Publication date: August 4, 2022Inventors: Hiroki MIYAKE, Tatsuji NAGAOKA
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Publication number: 20220230890Abstract: A method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting.Type: ApplicationFiled: December 15, 2021Publication date: July 21, 2022Inventors: SHUHEI ICHIKAWA, HIROKI MIYAKE
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Publication number: 20220189787Abstract: A manufacturing method of a semiconductor device includes: preparing a semiconductor substrate including a first semiconductor layer made of gallium oxide containing Sn and a second semiconductor layer disposed on the first semiconductor layer and made of n type gallium oxide having a Sn concentration lower than a Sn concentration of the first semiconductor layer; implanting ions of a group 2 element into the second semiconductor layer; and forming a diffusion region, in which the group 2 element diffuses, in a range from a surface of the second semiconductor layer to an interface between the second semiconductor layer and the first semiconductor layer.Type: ApplicationFiled: November 24, 2021Publication date: June 16, 2022Inventors: Shuhei ICHIKAWA, Hiroki MIYAKE
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Publication number: 20220181170Abstract: A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.Type: ApplicationFiled: November 9, 2021Publication date: June 9, 2022Inventors: Tatsuji NAGAOKA, Hiroki MIYAKE, Hiroyuki NISHINAKA, Yuki KAJITA, Masahiro YOSHIMOTO
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Publication number: 20220115544Abstract: A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.Type: ApplicationFiled: August 10, 2021Publication date: April 14, 2022Inventor: Hiroki MIYAKE
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Publication number: 20220093748Abstract: A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.Type: ApplicationFiled: August 10, 2021Publication date: March 24, 2022Inventor: Hiroki MIYAKE
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Patent number: 10840386Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.Type: GrantFiled: November 28, 2017Date of Patent: November 17, 2020Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hiroki Miyake, Yasushi Urakami, Yusuke Yamashita
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Patent number: 10605688Abstract: A load cell input unit capable of determining whether load cell connection cables have a broken line is provided. When the load cell input unit (30) is in a broken line detection mode, a voltage applying element (311) applies a voltage to distribution lines of an amplifying element (31), and a broken line determination element (33) determines whether the load cell connection cables (40) have a broken line based on a voltage measured by a load measuring element (32).Type: GrantFiled: December 12, 2016Date of Patent: March 31, 2020Assignee: OMRON CorporationInventors: Hitoshi Oba, Hiroki Miyake
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Patent number: 10551242Abstract: The present invention reduces the time required by measuring a sensor object more than before. An input unit (10) includes an acquisition portion (11) that acquires a time sequence signal, a filter portion (12) that filters the time sequence signal according to a frequency, a forwarding portion (13) that forwards a filtered signal by frequency to a control device (90) and a filter switching portion (14). The filter switching portion (14) switches whether the filter portion (12) filters the time sequence signal according to a frequency in the process of acquiring the time sequence signal by the acquisition portion (11).Type: GrantFiled: December 15, 2016Date of Patent: February 4, 2020Assignee: OMRON CorporationInventors: Hiroki Miyake, Toshiyuki Kojima
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Publication number: 20200020814Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.Type: ApplicationFiled: November 28, 2017Publication date: January 16, 2020Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hiroki MIYAKE, Yasushi URAKAMI, Yusuke YAMASHITA