Patents by Inventor Hiroki Nagasaki
Hiroki Nagasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230060917Abstract: A motor grader includes a front frame, a rear frame, an actuator that pivots the front frame with respect to the rear frame, an operator operation apparatus, a display apparatus, and a controller. The controller causes the display apparatus to show any one of an image showing a state of pivot and an image different from the image showing the state of pivot, based on a signal from the operator operation apparatus.Type: ApplicationFiled: December 24, 2020Publication date: March 2, 2023Applicant: KOMATSU LTD.Inventors: Yuki OKAMUNE, Hirohito HAGIWARA, Kengo YAMAMOTO, Hiroki NAGASAKI, Takeshi KAMIMAE
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Patent number: 7719040Abstract: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).Type: GrantFiled: July 27, 2006Date of Patent: May 18, 2010Assignee: Panasonic CorporationInventors: Hiroki Nagasaki, Shouzi Tanaka
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Publication number: 20090045407Abstract: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).Type: ApplicationFiled: July 27, 2006Publication date: February 19, 2009Inventors: Hiroki Nagasaki, Shouzi Tanaka
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Patent number: 7358105Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.Type: GrantFiled: December 2, 2005Date of Patent: April 15, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
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Patent number: 7317218Abstract: A solid-state imaging device can increase the amount of signal charge accumulation in a photodiode. The solid-state imaging device includes a gate electrode formed on a p-type semiconductor substrate. An n-type signal accumulation region accumulates the signal charge obtained through a photo-electrical conversion, and is formed in the semiconductor substrate so that a portion of the signal accumulation region is positioned below the gate electrode. An n-type drain region is positioned in the semiconductor substrate so that the n-type drain region is positioned opposite the signal accumulation region across the gate electrode. A p-type punch-through stopper region has a higher impurity concentration than the semiconductor substrate, and is formed in the semiconductor substrate so that the p-type punch-through region is positioned below the drain region, wherein an end of the punch-through stopper region is positioned closer to the signal accumulation region than the end of the drain region.Type: GrantFiled: November 2, 2005Date of Patent: January 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Syouji Tanaka, Ryohei Miyagawa, Kazunari Koga, Tatsuya Hirata, Hiroki Nagasaki
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Publication number: 20070221973Abstract: A solid-state imaging device includes: a plurality of photodiodes arranged in a matrix on a semiconductor substrate 1 for storing a signal charge converted from incident light; MOS transistors for reading the signal charge stored in the photodiode, an element isolation region for isolating the photodiode from the MOS transistors, an implanted isolation layer formed below the element isolation region, and an impurity region surrounding the photodiode, the sides and bottom of the element isolation region and the implanted isolation layer. The implanted isolation layer covers the sides and bottom of the element isolation region. The solid-state imaging device can efficiently suppress the sensitivity degradation caused by the outflow of electric charge.Type: ApplicationFiled: March 20, 2007Publication date: September 27, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroki Nagasaki, Shouzi Tanaka, Motonari Katsuno
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Patent number: 7157754Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.Type: GrantFiled: December 19, 2003Date of Patent: January 2, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
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Publication number: 20060157756Abstract: An object of the present invention is to provide a solid-state imaging device which can increase the amount of signal charge accumulation in a photodiode, and a manufacturing method thereof.Type: ApplicationFiled: November 2, 2005Publication date: July 20, 2006Inventors: Syouji Tanaka, Ryohei Miyagawa, Kazunari Koga, Tatsuya Hirata, Hiroki Nagasaki
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Publication number: 20060076582Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.Type: ApplicationFiled: December 2, 2005Publication date: April 13, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
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Publication number: 20050253214Abstract: Photodiodes 20a and 20b are formed in the main surface of the semiconductor substrate 10. The photodiode 20a includes a P+-type surface layer 22a and a charge accumulating portion 21a, and the photodiode 20b includes a P+-type surface layer 22b and a charge accumulating portion 21b. The photodiodes 20a and 20b are separated by an element isolating portion 33a having an STI structure. The bottom portions of the charge accumulating portions 21a and 21b constituting the photodiodes 20a and 20b are located in a deeper position from the main surface of the semiconductor substrate 10 than the bottom portions of the element isolating portion 33a. Thus, a solid-state imaging device in which color mixing can be prevented and the capacity of the charge accumulating portions is large, and the sensitivity and the saturation characteristics are excellent can be provided.Type: ApplicationFiled: January 24, 2005Publication date: November 17, 2005Inventors: Hiroki Nagasaki, Syouji Tanaka
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Patent number: 6920167Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.Type: GrantFiled: September 18, 2003Date of Patent: July 19, 2005Assignee: Sony CorporationInventors: Nozomu Hoshi, Hiroki Nagasaki
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Publication number: 20040173824Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.Type: ApplicationFiled: December 19, 2003Publication date: September 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
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Publication number: 20040137654Abstract: A semiconductor laser device having on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer is provided. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device comprises the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.Type: ApplicationFiled: September 18, 2003Publication date: July 15, 2004Applicant: Sony CorporationInventors: Nozomu Hoshi, Hiroki Nagasaki
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Patent number: 6654396Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.Type: GrantFiled: May 30, 2000Date of Patent: November 25, 2003Assignee: Sony CorporationInventors: Nozomu Hoshi, Hiroki Nagasaki
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Patent number: 6647045Abstract: There is provided a long-life and highly reliable air ridge type semiconductor laser device having a multi-layer structure including a first cladding layer of n-Al0.7GaInP, an active layer of AlGaAs, a second cladding layer of p-Al0.7GaInP and a contact (capping) layer of p-GaAs epitaxially grown in this sequential order on a substrate of n-GaAs, in which the contact layer and an upper portion of the second cladding layer is etched to be a ridge stripe, and the second cladding layer comprises an upper layer, which constitutes the ridge stripe together with the contact layer, and a lower layer having a thickness of 0.3 &mgr;m, which is positioned below the upper layer and extend outwardly from the both lower ends of the upper layer, and further, the semiconductor laser device includes a protection layer being an epitaxially grown n-GaAs layer having a film thickness of 0.Type: GrantFiled: September 13, 2001Date of Patent: November 11, 2003Assignee: Sony CorporationInventors: Koji Iwamoto, Hiroki Nagasaki
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Patent number: 6487226Abstract: A semiconductor light emitting device having a structure including an active layer between a p-type cladding layer and an n-type cladding layer on a base body comprises at least one of the p-type cladding layer and the n-type cladding layer has a lattice mismatch relative to the base body not smaller than 2.0×10−4 and not larger than 3.0×10−3 or not smaller than −1.5×10−3 and not larger than −2.0×10−4. Another semiconductor light emitting device comprises at least one of the p-type cladding layer and the n-type cladding layer and the active layer have a lattice mismatch relative to the base body not smaller than 2.0×10−4 and not larger than 3.0×10−3 or not smaller than −1.5×10−3 and not larger than −2.0×10−4.Type: GrantFiled: September 1, 1998Date of Patent: November 26, 2002Assignee: Sony CorporationInventors: Koji Iwamoto, Hiroki Nagasaki, Shoichiro Matsunaga, Shoji Hirata
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Publication number: 20020034204Abstract: There is provided a long-life and highly reliable air ridge type semiconductor laser device having a multi-layer structure including a first cladding layer of n-Al0.7GaInP, an active layer of AlGaAs, a second cladding layer of p-Al0.7GaInP and a contact (capping) layer of p-GaAs epitaxially grown in this sequential order on a substrate of n-GaAs, in which the contact layer and an upper portion of the second cladding layer is etched to be a ridge stripe, and the second cladding layer comprises an upper layer, which constitutes the ridge stripe together with the contact layer, and a lower layer having a thickness of 0.3 &mgr;m, which is positioned below the upper layer and extend outwardly from the both lower ends of the upper layer, and further, the semiconductor laser device includes a protection layer being an epitaxially grown n-GaAs layer having a film thickness of 0.Type: ApplicationFiled: September 13, 2001Publication date: March 21, 2002Inventors: Koji Iwamoto, Hiroki Nagasaki
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Patent number: 5953357Abstract: An AlGaInP-based buried-ridge semiconductor laser includes an n-type GaAs current blocking layer 8 buried in opposite sides of a ridge stripe portion 7 which is made of an upper-layer portion of a p-type AlGaInP cladding layer 4, p-type GaInP intermediate layer 5 and p-type GaAs contact layer 6. The ridge stripe portion 7 includes tapered regions 7a having the length of L1 at cavity-lengthwise opposite ends of the ridge stripe portion 7.Type: GrantFiled: August 28, 1997Date of Patent: September 14, 1999Assignee: Sony CorporationInventors: Shoji Hirata, Shiro Uchida, Koji Iwamoto, Hiroki Nagasaki, Tsuyoshi Tojyo