Patents by Inventor Hiroki Naraoka

Hiroki Naraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070052106
    Abstract: A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.
    Type: Application
    Filed: November 1, 2004
    Publication date: March 8, 2007
    Inventors: Kazumi Watase, Akio Nakamura, Minoru Fujisaku, Hiroki Naraoka, Takahiro Nakano
  • Patent number: 7154189
    Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: December 26, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
  • Patent number: 6905912
    Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: June 14, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
  • Publication number: 20050121761
    Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.
    Type: Application
    Filed: January 18, 2005
    Publication date: June 9, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
  • Publication number: 20030207492
    Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.
    Type: Application
    Filed: April 7, 2003
    Publication date: November 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
  • Patent number: 6582991
    Abstract: A semiconductor chip is mounted on a first surface of a substrate, the substrate having wiring formed on the first surface, so that a circuit formation surface of the semiconductor chip faces the first surface of the substrate and that electrodes provided on the circuit formation surface are connected with the wiring. A sealing resin layer is then formed on the first surface of the substrate to cover the semiconductor chip. The sealing resin layer and the semiconductor chip are ground starting from a surface opposite to the circuit formation surface to thin the semiconductor chip.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: June 24, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Maeda, Takashi Takata, Takao Ochi, Hiroki Naraoka, Takeshi Kawabata, Yoshiyuki Arai, Shigeru Nonoyama, Hajime Homma
  • Patent number: 6433285
    Abstract: The present invention provides a printed wiring board, an IC card module including the printed wiring board, and a method for fabricating the IC card module, for improving reliability of IC cards. The printed wiring board and the IC card module of the invention include: a base having a resin sealing region, clamped regions in a periphery zone of the resin sealing region clamped with a sealing mold, and non-clamped regions in the periphery zone; and terminals for external connection formed on the top surface of the base. The terminals are formed in a region other than any of the resin sealing region, the clamped regions, and the non-claimed regions.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: August 13, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Kenji Maeda, Takashi Takata, Hiroki Naraoka, Hajime Homma, Shigeru Nonoyama, Yoshiyuki Arai, Yuichiro Yamada, Fumito Ito
  • Publication number: 20010025721
    Abstract: The present invention provides a printed wiring board, an IC card module including the printed wiring board, and a method for fabricating the IC card module, for improving reliability of IC cards. The printed wiring board and the IC card module of the invention include: a base having a resin sealing region, clamped regions in a periphery zone of the resin sealing region clamped with a sealing mold, and non-clamped regions in the periphery zone; and terminals for external connection formed on the top surface of the base. The terminals are formed in a region other than any of the resin sealing region, the clamped regions, and the non-claimed regions.
    Type: Application
    Filed: December 14, 2000
    Publication date: October 4, 2001
    Inventors: Kenji Maeda, Takashi Takata, Hiroki Naraoka, Hajime Homma, Shigeru Nonoyama, Yoshiyuki Arai, Yuichiro Yamada, Fumito Ito