Abstract: A resonant gate driver 200A includes an H-bridge circuit and a resonant inductor integrated on a semiconductor substrate. A first leg of the H-bridge circuit includes a first high-side transistor, a first output node, and a first low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a first region defined along a first side. The second leg of the H-bridge circuit includes a second high-side transistor, a second output node, and a second low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a second region defined along a second side. A resonant inductor is a parasitic inductance that occurs in a coupling means that electrically couples the first output node and the second output node.

Abstract: A high-side driving circuit drives a high-side transistor configured as an N-channel or NPN transistor, according to an input signal. A level shift circuit level shifts the input signal. A latch stabilization circuit selects one node that corresponds to an output of the level shift circuit, from among a first node and a second node configured as complementary nodes provided to a latch circuit, and sinks a current from the node thus selected.

Abstract: A gate drive circuit in a switching circuit including a switching terminal connected to a node that is connected to a high-side transistor and a low-side transistor, and connected to an end of a boot-strap capacitor, a bootstrap terminal connected to another end of the bootstrap capacitor, a high-side driver having an output terminal connected to a gate of the high-side transistor, an upper power supply node connected to the bootstrap terminal, and a lower power supply node connected to the switching terminal, a low-side driver having an output terminal connected to a gate of the low-side transistor, a rectifying device for applying a constant voltage to the bootstrap terminal, and a dead time controller for controlling a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, based on a potential difference between the bootstrap terminal and the switching terminal.

Abstract: A switching circuit includes a high-side transistor and a low-side transistor, each of which is of an N-channel type. A switch and a rectifying element of a PMOS transistor are provided in series between a constant voltage line through which a constant voltage is supplied and a bootstrap line. A comparison circuit operates using a high-side power supply voltage, which is a potential difference between the bootstrap line and a switching line, as a power supply to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage. A level shift circuit level-shifts the detection signal down to a signal of which a ground voltage is low. A PMOS driver drives the switch asynchronously with switching of the low-side transistor in response to an output of the level shift circuit.

Abstract: A resonant gate driver 200A includes an H-bridge circuit and a resonant inductor integrated on a semiconductor substrate. A first leg of the H-bridge circuit includes a first high-side transistor, a first output node, and a first low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a first region defined along a first side. The second leg of the H-bridge circuit includes a second high-side transistor, a second output node, and a second low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a second region defined along a second side. A resonant inductor is a parasitic inductance that occurs in a coupling means that electrically couples the first output node and the second output node.

Abstract: A selection circuit generates a voltage VS of a switching terminal VS or a power supply voltage VCC, whichever is higher, in a common line. A regulator stabilizes a voltage VCOML of a reference line at a level lower than a voltage VCOM of the common line by a predetermined voltage difference ?V. A charge pump circuit is provided between the common line and the reference line and steps up a voltage difference ?V between the common line and the reference line. A rectifying element charges a bootstrap capacitor between a bootstrap terminal and the switching terminal, with an output voltage of the charge pump circuit.

Abstract: A gate drive circuit for use in a switching circuit including a high-side transistor and a low-side transistor that are connected in series to each other, includes a switching terminal connected to a node that is connected to the high-side transistor and the low-side transistor, and also connected to an end of a boot-strap capacitor; a bootstrap terminal connected to another end of the bootstrap capacitor; a high-side driver having an output terminal connected to a gate of the high-side transistor, an upper power supply node connected to the bootstrap terminal, and a lower power supply node connected to the switching terminal; a low-side driver having an output terminal connected to a gate of the low-side transistor; a rectifying device for applying a constant voltage to the bootstrap terminal; and a dead time controller for controlling a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, on the basis of a potential difference between the boo

Abstract: A high-side driving circuit drives a high-side transistor configured as an N-channel or NPN transistor, according to an input signal. A level shift circuit level shifts the input signal. A latch stabilization circuit selects one node that corresponds to an output of the level shift circuit, from among a first node and a second node configured as complementary nodes provided to a latch circuit, and sinks a current from the node thus selected.

Abstract: A driving circuit for an N-channel or NPN-type high-side transistor includes: a level shift circuit configured to level-shift an input signal; and a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit, wherein the level shift circuit includes: a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal; a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal.

Abstract: A selection circuit generates a voltage VS of a switching terminal VS or a power supply voltage VCC, whichever is higher, in a common line. A regulator stabilizes a voltage VCOML of a reference line at a level lower than a voltage VCOM of the common line by a predetermined voltage difference ?V. A charge pump circuit is provided between the common line and the reference line and steps up a voltage difference ?V between the common line and the reference line. A rectifying element charges a bootstrap capacitor between a bootstrap terminal and the switching terminal, with an output voltage of the charge pump circuit.

Abstract: A driving circuit for an N-channel or NPN-type high-side transistor includes: a level shift circuit configured to level-shift an input signal; and a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit, wherein the level shift circuit includes: a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal; a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal.

Abstract: A semiconductor integrated circuit includes a reference circuit including: a first NMOS transistor and a second NMOS transistor having a gate connected in common; and a resistor having one end connected to a source of the first NMOS transistor and the other end connected to a source of the second NMOS transistor, wherein the first NMOS transistor and the second NMOS transistor are formed of floating NMOS transistors

Abstract: A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse.

Abstract: A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse.

Abstract: A printing apparatus includes a print head that ejects ink for printing, an ink tank from which ink is fed to the print head, a first channel provided between the print head and the ink tank to feed ink in the ink tank to the print head, a second channel through which the ink in the first channel is transferred, and a pump connected to the second channel to transfer the ink in the first channel. The pump allows air or the ink in the first channel to be discharged via the second channel.

Abstract: A printing apparatus includes a print head that ejects ink for printing, an ink tank from which ink is fed to the print head, a first channel provided between the print head and the ink tank to feed ink in the ink tank to the print head, a second channel through which the ink in the first channel is transferred, and a pump connected to the second channel to transfer the ink in the first channel. The pump allows air or the ink in the first channel to be discharged via the second channel.