Patents by Inventor Hiroki Nikaido
Hiroki Nikaido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8247270Abstract: A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.Type: GrantFiled: May 13, 2009Date of Patent: August 21, 2012Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Hiroki Nikaido, Mitsuo Sugino
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Publication number: 20120199988Abstract: Disclosed is a method of manufacturing an electronic device, that includes obtaining a stack of the first electronic component and the second electronic component, while placing a resin layer which contains a flux-active compound and a thermosetting resin, between the first terminals and the second terminals; bonding the first terminals and the second terminals with solder, by heating the stack at a temperature not lower than the melting point of solder layers on the first terminals, while pressurizing the stack using a fluid; and curing the resin layer. The duration from the point of time immediately after the start of heating of the stack, up to the point of time when the temperature of the stack reaches the melting point of the solder layers, is set to 5 seconds or longer, and 15 minutes or shorter.Type: ApplicationFiled: October 13, 2010Publication date: August 9, 2012Applicant: Sumitomo Bakelite Co., Ltd.Inventors: Toru Meura, Hiroki Nikaido, Kenzou Maejima, Yoji Ishimura, Kenji Yoshida
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Publication number: 20120118939Abstract: The process for manufacturing the semiconductor device and the apparatus, which achieve stable production of semiconductor devices with improved connection reliability, is presented. First terminals of circuit boards 1 are arranged to face the corresponding bumps of semiconductor chips 2, respectively, and the resin layer 3 is disposed between the respective first terminals and the respective bumps to form laminates, and the laminates are simultaneously compressed from a direction of lamination, while heating a plurality of laminates. In such case, the diaphragm 54 disposed in a heating furnace 51 is abutted against a plurality of laminates or a member 531 to elastically deform the members while a plurality of laminates is heated in the heating furnace 51, so that laminates are simultaneously compressed from a direction of lamination, while heating thereof in a vacuum.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicants: SUMITOMO BAKELITE CO., LTD., ELPIDA MEMORY, INC.Inventors: Keiyo KUSANAGI, Koichi HATAKEYAMA, Mitsuhisa WATANABE, Yusuke NAKANOYA, Hidenori MATSUSHITA, Toru MEURA, Kenzou MAEJIMA, Hiroki NIKAIDO, Mina NIKAIDO
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Publication number: 20110221075Abstract: Provided is a method of manufacturing an electronic device comprising a first electronic component having a first terminal and a second electronic component having a second terminal, wherein said first electric component is electrically connected to said second electronic component by connecting said first terminal to said second terminal with solder, the method comprising, providing a resin layer having a flux action between said first terminal and said second terminal to obtain a laminate including said first electronic component, said second electronic component, and said resin layer, wherein a solder is provided on said first terminal or said second terminal; soldering said first terminal and said second terminal; and curing said resin layer while pressing said laminate with a pressurized fluid.Type: ApplicationFiled: October 30, 2009Publication date: September 15, 2011Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Toru Meura, Hiroki Nikaido, Mina Nikaido, Kenzou Maejima, Yoji Ishimura
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Publication number: 20110037174Abstract: A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.Type: ApplicationFiled: May 13, 2009Publication date: February 17, 2011Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Hiroki Nikaido, Mitsuo Sugino
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Patent number: 7470754Abstract: An objective of this invention is to provide an epoxy resin composition for encapsulating a semiconductor free from a harmful substance out of regard for the environment, which exhibits excellent soldering heat resistance and a higher productivity, as well as a semiconductor device manufactured by encapsulating therewith. This invention relates to a epoxy resin composition for encapsulating a semiconductor comprising, as essential components, (A) an epoxy resin having a particular structure and (B) a phenolic resin comprising a phenolic resin component having a particular structure as a main component, which contains a component having up to three aromatic rings in one molecule in 0.8% or less in an area ratio as determined by GPC analysis, as well as a semiconductor device manufactured by encapsulating a semiconductor chip with the composition.Type: GrantFiled: March 8, 2005Date of Patent: December 30, 2008Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Hiroki Nikaido, Hirofumi Kuroda
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Publication number: 20070196664Abstract: An epoxy resin composition for semiconductor encapsulation which has good solder heat resistance and excellent productivity, and a semiconductor device. An epoxy resin composition is described for semiconductor encapsulation comprising (A) an epoxy resin, (B) a phenolic resin, (C) (C-1) an organopolysiloxane having a carboxyl group and/or (C-2) a reaction product between an organopolysiloxane having a carboxyl group and an epoxy resin, and (D) a tri-fatty acid ester of glycerol.Type: ApplicationFiled: March 15, 2005Publication date: August 23, 2007Inventor: Hiroki Nikaido
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Publication number: 20050208307Abstract: An objective of this invention is to provide an epoxy resin composition for encapsulating a semiconductor free from a harmful substance out of regard for the environment, which exhibits excellent soldering heat resistance and a higher productivity, as well as a semiconductor device manufactured by encapsulating therewith. This invention relates to a epoxy resin composition for encapsulating a semiconductor comprising, as essential components, (A) an epoxy resin having a particular structure and (B) a phenolic resin comprising a phenolic resin component having a particular structure as a main component, which contains a component having up to three aromatic rings in one molecule in 0.8% or less in an area ratio as determined by GPC analysis, as well as a semiconductor device manufactured by encapsulating a semiconductor chip with the composition.Type: ApplicationFiled: March 8, 2005Publication date: September 22, 2005Inventors: Hiroki Nikaido, Hirofumi Kuroda
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Patent number: 6830825Abstract: An epoxy resin composition for encapsulation of semiconductors which contains substantially no halogen-based flame retarding agents or antimony compounds having properties of moldability, flame retardance, high-temperature storage characteristics, reliability for moisture resistance, and solder cracking resistance. The epoxy resin composition for encapsulating semiconductors contains (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, (D) an inorganic filler and (E) a phosphazene compound as essential components, the total weight of phosphate ion and phosphite ion contained in the phosphazene compound being not more than 500 ppm. Further, the epoxy resin composition may optionally contain a flame-retarding assistant or an ion scavenger.Type: GrantFiled: October 31, 2002Date of Patent: December 14, 2004Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Takafumi Sumiyoshi, Ayako Mizushima, Ken Oota, Yoshio Fujieda, Hiroki Nikaido, Takashi Aihara
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Publication number: 20030187107Abstract: The present invention provides an epoxy resin composition for encapsulation of semiconductors which contains substantially neither halogen-based flame retarding agents nor antimony compounds and is excellent in moldability, flame retardance, high-temperature storage characteristics, reliability for moisture resistance, and solder cracking resistance. That is, the present invention is an epoxy resin composition for encapsulating semiconductors which contains (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, (D) an inorganic filler and (E) a phosphazene compound as essential components, the total weight of phosphate ion and phosphite ion contained in the phosphazene compound being not more than 500 ppm. Further, the epoxy resin composition may optionally contain a flame-retarding assistant or an ion scavenger.Type: ApplicationFiled: October 31, 2002Publication date: October 2, 2003Inventors: Takafumi Sumiyoshi, Ayako Mizushima, Ken Oota, Yoshio Fujieda, Hiroki Nikaido, Takashi Aihara