Patents by Inventor Hiroki Sasano

Hiroki Sasano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114875
    Abstract: A manufacturing method of an animal litter box includes: a mold preparation process of preparing a mold for molding a resin molding product that forms at least a part of the animal litter box and has a urinary contact portion, the mold including an injection hole for injecting resin; a resin injecting process of injecting the resin from the injection hole; and a smoothing process of smoothing the resin of the urinary contact portion, the resin facing an inner opening of the injection hole, after the resin injecting process.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 11, 2024
    Applicant: Unicharm Corporation
    Inventors: Hiroki Yamamoto, Shinya Kaneko, Yasuhiro Sasano, Yasuhiro Akino
  • Patent number: 8133817
    Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
    Type: Grant
    Filed: November 30, 2008
    Date of Patent: March 13, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
  • Publication number: 20090170333
    Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
    Type: Application
    Filed: November 30, 2008
    Publication date: July 2, 2009
    Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
  • Patent number: 7498106
    Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: David S L Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20090032880
    Abstract: Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively etched in a first region of the substrate, such as a p-MOS region, using a first isotropic plasma etch process and a second anisotropic plasma etch process. In another embodiment, an at least partially isotropic plasma recess etch is performed to provide a recess adjacent to the channel region of the transistor. In a particular embodiment, the plasma etch process provides a recess sidewall that is neither positively sloped nor more than 10 nm re-entrant.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 5, 2009
    Inventors: Mark Naoshi Kawaguchi, Meihua Shen, Hiroki Sasano, Rong Chen
  • Patent number: 7482178
    Abstract: A method and apparatus for monitoring the stability of a substrate processing chamber and for adjusting the process recipe. Thickness and CD measurement data are collected before wafer processing and after wafer processing by an integrated or an in-situ metrology tool to monitor process chamber stability and to adjust the process recipe. The real time chamber stability monitoring enabled by the integrated metrology tool reduces the risk and cost of wafer mis-processing. The real time process recipe adjustment allows tightening of the process recipe. Process development cycle can also be reduced by the method and apparatus.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 27, 2009
    Assignee: Applied Materials, Inc.
    Inventors: David S. L. Mui, Wei Liu, Hiroki Sasano
  • Patent number: 7262865
    Abstract: A method and apparatus for controlling when a calibration cycle is started for a metrology tool. The method and apparatus exploits a correlation between a drift of a first parameter (e.g., film thickness measurement drift) and a drift of a second parameter (e.g., CD measurement drift). One embodiment of the method comprises measuring a film thickness on one or more reference substrates to determine when a drift component of these measurements exceeds a pre-determined range and thereafter calibrating the metrology tool when the drift component of the film thickness measurements exceeds the pre-determined range. Generally, the drift of the film thickness measurement will occur prior to substantial drift of the CD measurement occurring.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: August 28, 2007
    Assignee: Applied Materials, Inc.
    Inventors: David Mui, Hiroki Sasano, Wei Liu
  • Patent number: 7094613
    Abstract: Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: David Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20060091108
    Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 4, 2006
    Inventors: David Mui, Wei Liu, Hiroki Sasano
  • Patent number: 6960416
    Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: November 1, 2005
    Assignee: Applied Materials, Inc.
    Inventors: David S L Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20050190381
    Abstract: A method and apparatus for controlling when a calibration cycle is started for a metrology tool. The method and apparatus exploits a correlation between a drift of a first parameter (e.g., film thickness measurement drift) and a drift of a second parameter (e.g., CD measurement drift). One embodiment of the method comprises measuring a film thickness on one or more reference substrates to determine when a drift component of these measurements exceeds a pre-determined range and thereafter calibrating the metrology tool when the drift component of the film thickness measurements exceeds the pre-determined range. Generally, the drift of the film thickness measurement will occur prior to substantial drift of the CD measurement occurring.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: David Mui, Hiroki Sasano, Wei Liu
  • Patent number: 6924088
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: August 2, 2005
    Assignee: Applied Materials, Inc.
    Inventors: David S. L. Mui, Wei Liu, Shashank C. Deshmukh, Hiroki Sasano
  • Publication number: 20050085090
    Abstract: Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 21, 2005
    Inventors: David Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20050064714
    Abstract: A method for controlling dimensions of structures formed on a substrate using an etch process includes measuring pre-etch dimensions of the respective elements of a patterned etch mask and adjusting a process recipe of the etch process using the results of the pre-etch measurements. In one application, the method is used to control critical dimensions of a gate structure of a field effect transistor.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 24, 2005
    Inventors: David Mui, Wei Liu, Hiroki Sasano, Kyeongran Yoo
  • Patent number: 6858361
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile to adjust the next process the inspected wafer will undergo (e.g., a photoresist trim process). After the processing step, dimensions of a structure formed by the process, such as the CD of a gate formed by the process, are measured, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. By taking into account photoresist CD and profile variation when choosing a resist trim recipe, post-etch CD is decoupled from pre-etch CD and profile. With automatic compensation for pre-etch CD, a very tight distribution of post-etch CD is achieved. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: February 22, 2005
    Inventors: David S. L. Mui, Hiroki Sasano, Wei Liu
  • Publication number: 20050032250
    Abstract: A method and apparatus for monitoring the stability of a substrate processing chamber and for adjusting the process recipe. Thickness and CD measurement data are collected before wafer processing and after wafer processing by an integrated or an in-situ metrology tool to monitor process chamber stability and to adjust the process recipe. The real time chamber stability monitoring enabled by the integrated metrology tool reduces the risk and cost of wafer mis-processing. The real time process recipe adjustment allows tightening of the process recipe. Process development cycle can also be reduced by the method and apparatus.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 10, 2005
    Inventors: David Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20040038139
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
    Type: Application
    Filed: June 18, 2003
    Publication date: February 26, 2004
    Inventors: David S.L. Mui, Wei Liu, Shashank C. Deshmukh, Hiroki Sasano
  • Publication number: 20030228532
    Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.
    Type: Application
    Filed: May 1, 2003
    Publication date: December 11, 2003
    Applicant: Applied Materials, Inc.
    Inventors: David S.L. Mui, Wei Liu, Hiroki Sasano
  • Publication number: 20030165755
    Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile to adjust the next process the inspected wafer will undergo (e.g., a photoresist trim process). After the processing step, dimensions of a structure formed by the process, such as the CD of a gate formed by the process, are measured, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. By taking into account photoresist CD and profile variation when choosing a resist trim recipe, post-etch CD is decoupled from pre-etch CD and profile. With automatic compensation for pre-etch CD, a very tight distribution of post-etch CD is achieved. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment.
    Type: Application
    Filed: September 9, 2002
    Publication date: September 4, 2003
    Applicant: Applied Materials, Inc.
    Inventors: David S.L. Mui, Hiroki Sasano, Wei Liu