Abstract: A delay time counter in a DSP cyclically counts a sampling clock from zero to a delay time sampling count and issues a delay time interrupt to a CPU each time the sampling clock count reaches the delay time sampling count. The CPU measures a time difference between each time the DSP issues the delay time interrupt and each time sequence clock interrupts occur a number of times corresponding to the delay time. Then, in order to reduce this time difference, the CPU increases or decreases a maximum count that is set to the sequence clock counter. Therefore, in the next delay process, the shift between the time by which the automatic performance is advanced by the CPU (which is equal to the delay time) and the timing of the delay process executed by the DSP (which is also equal in length to the delay time) will be corrected.

Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.

Abstract: A solid electrolytic capacitor according to the present invention includes: an anode body; a dielectric layer arranged on a surface of the anode body; and a solid electrolyte layer arranged on a surface of the dielectric layer and formed using zinc oxide having a conductivity of 1 (S/cm) or more. Further, in the solid electrolytic capacitor according to the present invention, a diffusion suppressing layer to suppress a mutual diffusion between the dielectric layer and the solid electrolyte layer may be formed between the dielectric layer and the solid electrolyte layer.

Abstract: An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

Abstract: The present invention provides a thermoelectric conversion material represented by the following chemical formula Mg3+mAaBbD2-eEe. The element A represents at least one selected from the group consisting of Ca, Sr, Ba and Yb. The element B represents at least one selected from the group consisting of Mn and Zn. The value of m is not less than ?0.39 and not more than 0.42. The value of a is not less than 0 and not more than 0.12. The value of b is not less than 0 and not more than 0.48. The element D represents at least one selected from the group consisting of Sb and Bi. The element E represents at least one selected from the group consisting of Se and Te. The value of e is not less than 0.001 and not more than 0.06. The thermoelectric conversion material has a La2O3 crystalline structure. The thermoelectric conversion material is of n-type. The present invention provides a novel thermoelectric conversion material.

Abstract: A motor control unit (a motor control apparatus) performs driving control for a stepping motor by using vector control, and detects a rotational position ? of a rotor of the stepping motor, the rotational position ? being required for vector control, by using a position detection unit, based on a pulse signal that is output from an encoder. The motor control unit determines whether or not there is an abnormality in the pulse signal output from the encoder, by using an abnormality determination unit. Upon determining that there is an abnormality in the pulse signal, the motor control unit corrects a detection value of the position ? of the rotor of the stepping motor so as to compensate an error caused by the abnormality in the pulse signal, by using the position detection unit.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.

Abstract: The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back-side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back-side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back-side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back-side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A full-automatic washing machine includes: a first control part, a receiving part, a body display part arranged on an upper panel, and a remote controller separated from the body display part. The remote controller includes: setting keys for setting operating information of a washing operation, a second control part, an information display part and a transmitting part. The second control part displays operating information set by the setting keys through the information display part, and transmits the operating information by the transmitting part to the receiving part through wireless communication. A mode display part of the body display part is illuminated in a color such as blue corresponding to the reception of the operating information until the washing operation starts when the first control part receives the operating information.

Abstract: An imaging apparatus including a pixel, a current source, and a signal processing circuit. The pixel outputs signal charge, obtained by imaging, as a pixel signal. The current source is connected to a transmission path for the pixel signal and has a variable current. The signal processing circuit performs signal processing on a signal depending on an output signal to the transmission path and performs control so that a current of the current source is changed in accordance with the result of signal processing.

Abstract: Provided is a technique for computing a brain function index for diagnosing a mental disorder at the individual level, which can be applied to even a child around school age. A brain function index computing device includes a brain activity value calculation processing unit configured to calculate from brain activity signals of a subject a first brain activity value of a region including the meddle frontal gyrus (MFG) and a second brain activity value of a region including the inferior frontal gyrus (IFG); and a brain function index calculation processing unit configured to calculate a brain function index associated with a mental disorder using the first brain activity value and the second brain activity value.

Abstract: A vacuum thermally bonding apparatus is provided, in which while air is being prevented in vacuum from entering a bonding layer, an element is thermally bonded to a substrate under vacuum by forming the bonding layer having a good thickness under an appropriate pressing pressure, while suppressing runout of the adhesive as much as possible, with a pressing force being slightly adjustable. A lower end portion of an upper frame member is gas-tightly slidably sealed to a peripheral portion of the lower plate member to form a vacuum partition wall therein, and a pressurizing release film is contacted with an upper face of the element, and thermally softened in the atmospheric pressure.

Abstract: A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A trialkylsilane-based silicon precursor compound may be expressed by Si(Ri)X, i=1-3, where each of “R1”, “R2”, and “R3” is a hydrogen or an alkyl having 1-5 carbon(s), all of “R1”, “R2”, and “R3” are not hydrogen, “X” is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R*)3, and “R*” is a hydrogen or an alkyl group having 1˜5 carbon(s).