Abstract: According to one embodiment, a radar device comprises a panel including clusters and a controller. The controller is configured to cause a first cluster of the clusters to transmit an electromagnetic wave to a target, cause the first cluster and at least one second cluster adjacent to the first cluster to receive a reflected wave from the target, and cause the first cluster and the at least one second cluster to output a reception signal. At least one cluster other than the first cluster and other than the at least one second cluster does not output the reception signal.

Abstract: According to one embodiment, an inspection system includes an estimation device and a detection device. The estimation device is configured to estimate an inspection range having a possibility that a predetermined object is present. The detection device is configured to generate detection information as to whether or not the predetermined object is present in the inspection range.

Abstract: According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface.

Abstract: According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface.

Abstract: A semiconductor modules includes insulating substrates having first and second patterns thereon. One terminal plate connects the first patterns and another terminal plate connects the second patterns. A first and a second switching chip are provided on the first pattern. Bonding wires connect the first ans second chips to the second pattern. An insulating plate with an auxillary conductor theron is disposed on the first pattern between the second pattern and both the first and second chips. A first auxiliary connection connect the auxiliary conductor and the second chip and a second auxilliary connection connect thes auxiliary conductor and the second pattern. The auxiliary connections may be, for example, bonding wires or solder connections.

Abstract: A semiconductor device includes a substrate joined to a base by a first junction material and a semiconductor element joined to the substrate by a second junction material. At least one of the first and second junction materials comprises tin, antimony, and cobalt. In some embodiments, the junction materials comprise cobalt having a weight percentage between 0.05 wt % and 0.2 wt %, antimony with a weight percentage between 1 wt % and 10 wt %, and the balance being substantially tin.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element and a metal film. The semiconductor element has a first surface and a second surface opposite to the first surface. The metal film is provided above the second surface of the semiconductor element. The metal film includes Cr.

Abstract: A method for fabricating a power semiconductor device that comprises a base substrate with a conductive layer on a surface of the base substrate and semiconductor components mounted on the base substrate includes forming a hardened layer on the surface of the conductive layer before mounting a semiconductor component on the base substrate. The forming of the hardened layer may optionally be performed using a peening process, for example, a shot peening process, a laser peening process, or an ultrasonic peening process. The conductive layer may comprise a metal such as, for example, aluminum or copper.

Abstract: To provide an inverter unit with excellent manufacturing performance and with current carrying capacity increased and size reduced by further increasing the cooling efficiency of a power efficiency device. The inverter unit includes: a semiconductor chip constituting an arm of an inverter; a first conductor 33 joined to a positive side of the semiconductor chip; and a second conductor 35 joined to a negative side of the semiconductor chip. The first and second conductors are disposed above a cooler 22 cooling the semiconductor chip so that a joint surface of the first conductor 33 which is joined to a positive electrode of the semiconductor chip and a joint surface of the second conductor 35 which is joined to a negative electrode of the semiconductor chip are not in parallel to a surface of the cooler 22.

Abstract: A semiconductor device includes: a semiconductor element (106) having a surface on a positive electrode side and a surface on a negative electrode side; multiple conductors (13 to 15) bonded respectively to the surface on the positive electrode side and to the surface on the negative electrode side of the semiconductor element; a heat sink plate (11) disposed as intersecting a junction interface between the semiconductor element and each of the multiple conductors and configured to discharge heat of the semiconductor element; and an insulator (12) bonding the heat sink plate to the multiple conductors. The insulator includes a heat conductive insulator (16) disposed inside a portion facing all of the multiple conductors and a flexible insulator (17) disposed at a portion other than the heat conductive insulator.

Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor said first conductor and second conductor are connected connected to said wide conductor; and a cooler to which through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.

Abstract: To provide an inverter unit with excellent manufacturing performance and with current carrying capacity increased and size reduced by further increasing the cooling efficiency of a power efficiency device. The inverter unit includes: a semiconductor chip constituting an arm of an inverter; a first conductor 33 joined to a positive side of the semiconductor chip; and a second conductor 35 joined to a negative side of the semiconductor chip. The first and second conductors are disposed above a cooler 22 cooling the semiconductor chip so that a joint surface of the first conductor 33 which is joined to a positive electrode of the semiconductor chip and a joint surface of the second conductor 35 which is joined to a negative electrode of the semiconductor chip are not in parallel to a surface of the cooler 22.

Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.

Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.

Abstract: In an inverter apparatus in which a three-phase inverter main circuit having a plurality of arms comprises a plurality of semiconductor chips for electric power, one arm of the three-phase inverter main circuit includes IGBTs and diodes of semiconductor chips having a size of 10 mm by 10 mm or less with the semiconductor chips connected in parallel, while the IGBTs and the diodes are bonded to a conductor having a thickness of 1.5 mm or more and 5 mm or less, and the conductor is glued to a cooler through an insulating resin sheet containing ceramics.

Abstract: An enameled wire capable of improving withstand lifetime with respect to the application of surge voltage of an inverter and thermal degradation thereof while restricting an amount of an inorganic filler material is provided. The enameled wire includes an electrically conductive wire (11) and a coating (12) formed of a high molecular compound uniformly mixed with an inorganic filler material in the form of fine flat particles provided around the electrically conductive wire (11). The enameled wire may include an electrically conductive wire (21), a coating (23) formed of a polyester imide resin solution mixed with an inorganic filler material in the form of fine flat particles and provided on the conductive wire and a coating (24) formed of polyamide imide and provided on the coating (23).

Abstract: By molding a plurality of vacuum valves (7), (13) having differing functions together with an input member (3) and an output member (21) en bloc in a resin layer (23) to form a switch gear (1), the present invention seeks to achieve dielectric strength without resorting to the use of SF6 gas, while rendering the whole device more compact and reducing both the number of parts and the man hours required for molding.

Abstract: By providing a plurality of semiconductor chips that are connected in parallel and constitute one arm of an inverter; a first conductor to which a face on one side of said plurality of semiconductor chips is connected; a wide conductor to which a face on the other side of said plurality of semiconductor chips is connected; a second conductor connected to said wide conductor; and a cooler to which said first conductor and second conductor are connected through an insulating resin sheet, part of the heat loss generated in the semiconductor chips is thermally conducted to the first conductor and is thence thermally conducted to the cooler, producing cooling, while another part thereof is thermally conducted to the wide conductor and thence to the second conductor, whence it is thermally conducted to the cooler, producing cooling.

Abstract: An enameled wire capable of improving withstand lifetime with respect to the application of surge voltage of an inverter and thermal degradation thereof while restricting an amount of an inorganic filler material is provided. The enameled wire comprises an electrically conductive wire (11) and a coating (12) formed of a high molecular compound uniformly mixed with an inorganic filler material in the form of fine flat particles provided around the electrically conductive wire (11). The enameled wire may comprise an electrically conductive wire (21), a coating (23) formed of a polyester imide resin solution mixed with an inorganic filler material in the form of fine flat particles and provided on the conductive wire and a coating (24) formed of polyamide imide and provided on the coating (23).

Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.