Patents by Inventor Hiroki Shinkawata
Hiroki Shinkawata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11705361Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.Type: GrantFiled: July 7, 2021Date of Patent: July 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hitoshi Maeda, Tatsuyoshi Mihara, Hiroki Shinkawata
-
Publication number: 20220068706Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.Type: ApplicationFiled: July 7, 2021Publication date: March 3, 2022Inventors: Hitoshi MAEDA, Tatsuyoshi MIHARA, Hiroki SHINKAWATA
-
Patent number: 10790355Abstract: In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.Type: GrantFiled: June 23, 2017Date of Patent: September 29, 2020Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Patent number: 10008429Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.Type: GrantFiled: October 19, 2017Date of Patent: June 26, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki Shinkawata
-
Publication number: 20180040523Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.Type: ApplicationFiled: October 19, 2017Publication date: February 8, 2018Inventor: Hiroki SHINKAWATA
-
Publication number: 20170373145Abstract: In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.Type: ApplicationFiled: June 23, 2017Publication date: December 28, 2017Applicant: Renesas Electronics CorporationInventor: Hiroki SHINKAWATA
-
Patent number: 9824945Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.Type: GrantFiled: March 3, 2016Date of Patent: November 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki Shinkawata
-
Publication number: 20160293507Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.Type: ApplicationFiled: March 3, 2016Publication date: October 6, 2016Inventor: Hiroki SHINKAWATA
-
Publication number: 20150287746Abstract: In a step F2, an isolation region and an element formation region are formed in an SOI substrate. In a step F3, an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F4, a gate electrode is formed. In a step F5, extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F6, an elevated epitaxial layer is formed in the SOI region.Type: ApplicationFiled: March 31, 2015Publication date: October 8, 2015Inventors: Hiroki SHINKAWATA, Toshiaki IWAMATSU
-
Patent number: 8647944Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: GrantFiled: June 26, 2013Date of Patent: February 11, 2014Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Patent number: 8604553Abstract: The present invention, in a method for manufacturing a semiconductor device having an n-channel transistor and a p-channel transistor each of which has an insulation film of a high electric permittivity, inhibits a foreign matter from adhering to the side of a gate insulation film of the n-channel transistor. Over the main surface of a semiconductor substrate, a functional n-channel transistor is formed in a p-type impurity region and a functional p-channel transistor is formed in an n-type impurity region. A plurality of first peripheral transistors formed in the region other than the functional n-channel transistor in the p-type impurity region are formed so that a peripheral n-type structure and a peripheral p-type structure may coexist in a planar view.Type: GrantFiled: January 9, 2012Date of Patent: December 10, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Publication number: 20130288437Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Inventor: Hiroki Shinkawata
-
Patent number: 8492813Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: GrantFiled: September 23, 2011Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Patent number: 8367432Abstract: To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off.Type: GrantFiled: July 5, 2010Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Publication number: 20120187500Abstract: The present invention, in a method for manufacturing a semiconductor device having an n-channel transistor and a p-channel transistor each of which has an insulation film of a high electric permittivity, inhibits a foreign matter from adhering to the side of a gate insulation film of the n-channel transistor. Over the main surface of a semiconductor substrate, a functional n-channel transistor is formed in a p-type impurity region and a functional p-channel transistor is formed in an n-type impurity region. A plurality of first peripheral transistors formed in the region other than the functional n-channel transistor in the p-type impurity region are formed so that a peripheral n-type structure and a peripheral p-type structure may coexist in a planar view.Type: ApplicationFiled: January 9, 2012Publication date: July 26, 2012Inventor: Hiroki SHINKAWATA
-
Patent number: 8211716Abstract: The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.Type: GrantFiled: March 13, 2009Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Publication number: 20120012936Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicant: Renesas Technology Corp.Inventor: Hiroki SHINKAWATA
-
Patent number: 8058679Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: GrantFiled: February 11, 2011Date of Patent: November 15, 2011Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata
-
Publication number: 20110133293Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: ApplicationFiled: February 11, 2011Publication date: June 9, 2011Applicant: Renesas Technology Corp.Inventor: Hiroki SHINKAWATA
-
Patent number: 7919799Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.Type: GrantFiled: December 11, 2007Date of Patent: April 5, 2011Assignee: Renesas Electronics CorporationInventor: Hiroki Shinkawata