Patents by Inventor Hiroki Sudo
Hiroki Sudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250148095Abstract: A secure computation apparatus includes a former half window frame column generation unit configured to generate, with respect to subVector ({g?}, s+1, i}, a bit column obtained by an OR operation performed on all bits from the end to each position as {wf?}, a latter half window frame column generation unit configured to generate, with respect to subVector ({g?}, i+1, t}, a bit column obtained by an OR operation performed on all bits from the head to each position as {wl?}, a window frame flag column generation unit configured to generate {w?} by combining {wf?} and {wl?}, an inverted window frame flag column generation unit configured to generate {w??} by performing a NOT operation on {w?}, a share conversion unit configured to convert {w??} into [[w??]], and a product-sum operation unit configured to execute a product-sum operation on subVector ([[v??]], s, t) and [[w??]].Type: ApplicationFiled: February 16, 2022Publication date: May 8, 2025Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventor: Hiroki SUDO
-
Publication number: 20250150265Abstract: The secure computation apparatus includes: a former half window frame column generation unit configured to generate, with respect to a vector subVector ({g?}, s+1, i} obtained by extracting elements from an (s+1)-th element to an i-th element of {g?}, a bit column obtained by an OR operation performed on all bits from the end to each position as a former half window frame flag column {wf?}; a latter half window frame column generation unit configured to generate, with respect to a vector subVector ({g?}, i+1, t} obtained by extracting elements from an (i+1)-th element to a t-th element of {g?}, a bit column obtained by calculating OR of all bits from the head to each position as a latter half window frame flag column {wl?}; and a window frame flag column generation unit configured to generate a window frame flag column {w?} by combining the former half window frame flag column {wf?} from the front side and the latter half window frame flag column {wl?} from the rear side having {0} interposed therebetween.Type: ApplicationFiled: February 16, 2022Publication date: May 8, 2025Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventor: Hiroki SUDO
-
Publication number: 20250131855Abstract: A secure computation device 1n of a secure computation system according to an aspect of this invention includes a first calculation unit 11n, a second calculation unit 12n, a third calculation unit 13n, a fourth calculation unit 14n, a fifth calculation unit 15n, a sixth calculation unit 16n, a seventh calculation unit 17n, and an output unit 18n. By calculation being performed in cooperation of these, a group by count operation can be performed on a table to which a flag is added.Type: ApplicationFiled: July 8, 2021Publication date: April 24, 2025Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Ryo KIKUCHI, Dai IKARASHI, Hiroki SUDO
-
Publication number: 20240424615Abstract: Provided are a solder, a solder alloy, a solder ball, a solder paste, and a solder joint, which have a low melting point, high hardness in a high-temperature environment, heat cycle resistance, and electromigration resistance. The solder alloy has an alloy composition that includes, by mass %, Bi: 30 to 60%, Ag: 0.7 to 2.0%, Cu: more than 0% and 1.00% or less, Ni: 0.01 to 1.00%, Sb: 0.2 to 1.5%, with the balance being Sn.Type: ApplicationFiled: September 4, 2024Publication date: December 26, 2024Inventors: Takahiro Matsufuji, Shunsaku Yoshikawa, Hiroki Sudo
-
Patent number: 12109653Abstract: Provided are a solder, a solder alloy, a solder ball, a solder paste, and a solder joint, which have a low melting point, high hardness in a high-temperature environment, heat cycle resistance, and electromigration resistance. The solder alloy has an alloy composition that includes by mass %, Bi: 30 to 60%, Ag: 0.7 to 2.0%, Cu: more than 0% and 1.00% or less, Ni: 0.01 to 1.00%, Sb: 0.2 to 1.5%, with the balance being Sn.Type: GrantFiled: July 21, 2023Date of Patent: October 8, 2024Assignee: Senju Metal Industry Co., Ltd.Inventors: Takahiro Matsufuji, Shunsaku Yoshikawa, Hiroki Sudo
-
Patent number: 12095906Abstract: The present invention provides techniques to calculate the number of surviving and the number of deaths while still concealing survival time data. The present invention includes: a group data position calculation means configured to calculate a share [[gA]] of a sequence gA and a share [[gB]] of a sequence gB represented by predetermined equations from a share [[g]] of a sequence g of values of group of survival time data included in a survival time data set D; a group data number calculation means configured to calculate a share [[sA]] and a share [[sB]] from a share [[t]] of a sequence t of values of time of survival time data included in the survival time data set D, the share [[gA]], and the share [[gB]], by [[sA]]=GroupSum ([[gA]], [[t]]), [[sB]]=GroupSum ([[gB]], [[t]]); and a survival number calculation means.Type: GrantFiled: October 2, 2019Date of Patent: September 17, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Atsunori Ichikawa, Dai Ikarashi, Koki Hamada, Ryo Kikuchi, Hiroki Sudo, Ibuki Mishina
-
Publication number: 20240273219Abstract: By using [x0,0], . . . , [x0,r(0)-1], . . . , [xL-1,0], . . . , [xL-1,r(L-1)-1] obtained by concealing L sets X0={x0,0, . . . , x0,r(0)-1}, . . . , XL-1={xL-1,0, . . . , xL-1,r(L-1)-1}, [c0], . . . , [cm-1] obtained by concealing the number cp of elements representing kp among x0,0, . . . , x0,r(0)-1, . . . , xL-1,0, . . . , xL-1,r(L-1)-1 for p=0, . . . , m?1 are obtained, [eq0], . . . , [eqm-1] obtained by concealing eqp=T when cp is L and eqp=F when cp is not L for p=0, . . . , m?1 are obtained, and a data structure including [kp] and [eqp] associated with each other is output as a concealed operation result of a product set of X0, . . . , XL-1.Type: ApplicationFiled: June 8, 2021Publication date: August 15, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Hiroki SUDO, Dai IKARASHI
-
Publication number: 20240273180Abstract: A concealed operation result indicating concealed information of an Intersect operation result of X and Y is obtained while X={{x0, . . . , xn?1}} and Y={{y0, . . . , ym?1}} are concealed. A secure computation device obtains a sequence ([s], [M]) including [s] including n [B0] and m [B1] and [M] including [x0], . . . , [xn?1] and [y0], . . . , [ym?1], performs stable sorting on the sequence ([s], [M]) according to an order relationship of content represented by each of the elements M0, . . . , Mn+m?1 to obtain a sequence ([s?], [M?]), obtain [eqq] where eqq=T when M?q=M?q+1 and eqq=F otherwise and [seqq] where seqq=T when s?q=s?q+1 and seqq=F otherwise, obtain [fq] where fq=D1 when eqq=T and seqq=F and fq=D0 otherwise, and outputs [fq] and [M?q]. Where, [?] is concealed information of ?.Type: ApplicationFiled: June 4, 2021Publication date: August 15, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Hiroki SUDO, Dai IKARASHI
-
Publication number: 20240184577Abstract: A secure computation device 1n of the secure computation system includes a first calculation unit 11n, a second calculation unit 12n, a third calculation unit 13n, a fourth calculation unit 14n, and an output unit 15n. By calculation being performed in cooperation of these, a group by max operation or a group by min operation can be performed on a table to which a flag is added.Type: ApplicationFiled: July 8, 2021Publication date: June 6, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Ryo KIKUCHI, Dai IKARASHI, Hiroki SUDO
-
Publication number: 20240100635Abstract: A core material has a core 12; a solder layer 16 made of a (Sn—Bi)-based solder alloy provided on an outer side of the core 12; and a Sn layer 20 provided on an outer side of the solder layer 16. The core contains metal or a resin. When a concentration ratio of Bi contained in the solder layer 16 is a concentration ratio (%)=a measured value of Bi (% by mass)/a target Bi content (% by mass), or a concentration ratio (%)=an average value of measured values of Bi (% by mass)/a target Bi content (% by mass), the concentration ratio is 91.4% to 106.7%. The thickness of the Sn layer 20 is 0.215% or more and 36% or less of the thickness of the solder layer 16.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: SENJU METAL INDUSTRY CO., LTD.Inventors: Shigeki Kondoh, Masato Tsuchiya, Hiroki Sudo, Hiroshi Okada, Daisuke Souma
-
Publication number: 20240061904Abstract: A secure computation apparatus (1) included in a secure relational algebraic operation system performs secure computation of a composite of a first relational algebraic operation and a second relational algebraic operation on an operation target input table. A ciphertext of an operation target table is input to an input unit (11). A first relational algebraic operation unit (12) performs secure computation of the first relational algebraic operation on the input table. A valid row extraction unit (13) generates an intermediate table obtained by extracting a valid row from an operation result of the first relational algebraic operation. A second relational algebraic operation unit (14) performs secure computation of the second relational algebraic operation on the intermediate table. An output unit (15) outputs an operation result of the second relational algebraic operation.Type: ApplicationFiled: January 13, 2021Publication date: February 22, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Hiroki SUDO, Dai IKARASHI
-
Publication number: 20240024990Abstract: Provided are a solder, a solder alloy, a solder ball, a solder paste, and a solder joint, which have a low melting point, high hardness in a high-temperature environment, heat cycle resistance, and electromigration resistance. The solder alloy has an alloy composition by mass %, Bi: 30 to 60%, Ag: 0.7 to 2.0%, Cu: more than 0% and 1.00% or less, Ni: 0.01 to 1.00%, Sb: 0.2 to 1.5%, with the balance being Sn.Type: ApplicationFiled: July 21, 2023Publication date: January 25, 2024Inventors: Takahiro Matsufuji, Shunsaku Yoshikawa, Hiroki Sudo
-
Patent number: 11872656Abstract: A core material has a core 12; a solder layer 16 made of a (Sn—Bi)-based solder alloy provided on an outer side of the core 12; and a Sn layer 20 provided on an outer side of the solder layer 16. The core contains metal or a resin. When a concentration ratio of Bi contained in the solder layer 16 is a concentration ratio (%)=a measured value of Bi (% by mass)/a target Bi content (% by mass), or a concentration ratio (%)=an average value of measured values of Bi (% by mass)/a target Bi content (% by mass), the concentration ratio is 91.4% to 106.7%. The thickness of the Sn layer 20 is 0.215% or more and 36% or less of the thickness of the solder layer 16.Type: GrantFiled: September 30, 2020Date of Patent: January 16, 2024Assignee: SENJU METAL INDUSTRY CO., LTD.Inventors: Shigeki Kondoh, Masato Tsuchiya, Hiroki Sudo, Hiroshi Okada, Daisuke Souma
-
Publication number: 20230173619Abstract: Provided are a lead-free and antimony-free solder alloy which has a medium-low melting point and ensures solderability even after being held at a high temperature for a long time, a solder ball, a ball grid array, and a solder joint. The lead-free and antimony-free solder alloy has an alloy composition consisting of 12 to 23% by mass of In, and 0.001 to 0.08% by mass of Ge, with the balance being Sn and unavoidable impurities. Preferably, the alloy composition has 16 to 21% by mass of In; the alloy composition has 0.005 to 0.01% by mass of Ge; the alloy composition has 0.005 to 0.009% by mass of Ge; U and Th as the unavoidable impurities are each included in an amount of 5 mass ppb or less; and As and Pb as the unavoidable impurities are each included in an amount of 5 mass ppm or less.Type: ApplicationFiled: April 29, 2021Publication date: June 8, 2023Inventors: Takashi Saito, Hiroki Sudo, Mai Susa
-
Publication number: 20220413802Abstract: A computation apparatus, a method of the same, and a program which perform a secure computation using fixed-point arithmetic, and overflow is unlikely to occur and the occurrence of division by zero can be detected when an odds ratio is calculated. The computation apparatus includes an odds ratio computation unit for obtaining an odds ratio between a first group (a+b) and a second group (c+d) based on four plaintext values a, b, c, and d, by means of secure computation; a zero-division detection unit for determining, by means of secure computation, whether or not at least one of the plaintext values b and c is not zero, and detecting division by zero; and a selection unit for selecting the odds ratio if division by zero is not detected, by means of secure computation.Type: ApplicationFiled: October 7, 2019Publication date: December 29, 2022Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Hiroki SUDO, Dai IKARASHI, Koki HAMADA, Ryo KIKUCHI, Atsunori ICHIKAWA, Ibuki MISHINA
-
Publication number: 20220360431Abstract: The present invention provides techniques to calculate the number of surviving and the number of deaths while still concealing survival time data. The present invention includes: a group data position calculation means configured to calculate a share [[gA]] of a sequence gA and a share [[gB]] of a sequence gB represented by predetermined equations from a share [[g]] of a sequence g of values of group of survival time data included in a survival time data set D; a group data number calculation means configured to calculate a share [[sA]] and a share [[sB]] from a share [[t]] of a sequence t of values of time of survival time data included in the survival time data set D, the share [[gA]], and the share [[gB]], by [[sA]]=GroupSum ([[gA]], [[t]]), [[sB]]=GroupSum ([[gB]], [[t]]); and a survival number calculation means.Type: ApplicationFiled: October 2, 2019Publication date: November 10, 2022Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Atsunori ICHIKAWA, Dai IKARASHI, Koki HAMADA, Ryo KIKUCHI, Hiroki SUDO, Ibuki MISHINA
-
Patent number: 11478869Abstract: A method includes applying a first flux onto an electrode provided on a substrate and placing a solder material on the electrode, heating the substrate to form a solder bump on the electrode, deforming the solder bump to provide a flat surface or a depressed portion on the solder bump, applying a second flux to the solder bump; placing a core material on the solder bump, the core material including a core portion and a solder layer that covers a surface of the core portion, and heating the substrate to join the core material to the electrode by the solder bump and the solder layer.Type: GrantFiled: June 3, 2021Date of Patent: October 25, 2022Assignee: SENJU METAL INDUSTRY CO., LTD.Inventors: Takahiro Hattori, Hiroki Sudo, Hiroshi Okada, Daisuke Souma
-
Publication number: 20220212294Abstract: A core material has a core 12; a solder layer 16 made of a (Sn—Bi)-based solder alloy provided on an outer side of the core 12; and a Sn layer 20 provided on an outer side of the solder layer 16. The core contains metal or a resin. When a concentration ratio of Bi contained in the solder layer 16 is a concentration ratio (%)=a measured value of Bi (% by mass)/a target Bi content (% by mass), or a concentration ratio (%)=an average value of measured values of Bi (% by mass)/a target Bi content (% by mass), the concentration ratio is 91.4% to 106.7%. The thickness of the Sn layer 20 is 0.215% or more and 36% or less of the thickness of the solder layer 16.Type: ApplicationFiled: September 30, 2020Publication date: July 7, 2022Applicant: SENJU METAL INDUSTRY CO., LTD.Inventors: Shigeki KONDOH, Masato TSUCHIYA, Hiroki SUDO, Hiroshi OKADA, Daisuke SOUMA
-
Patent number: 11344976Abstract: The present invention provides a solder material containing Sn or a Sn-containing alloy and 40 to 320 ppm by mass of A, the solder material including an As-enriched layer.Type: GrantFiled: November 21, 2018Date of Patent: May 31, 2022Assignee: SENJU METAL INDUSTRY CO., LTD.Inventors: Hiroyoshi Kawasaki, Hiroki Sudo, Takahiro Roppongi, Hiroshi Okada, Daisuke Soma, Takashi Akagawa, Hiroshi Takahashi, Hiroshi Kawanago, Satoshi Yokota, Osamu Munekata
-
Publication number: 20210387276Abstract: A method includes applying a first flux onto an electrode provided on a substrate and placing a solder material on the electrode, heating the substrate to form a solder bump on the electrode, deforming the solder bump to provide a flat surface or a depressed portion on the solder bump, applying a second flux to the solder bump; placing a core material on the solder bump, the core material including a core portion and a solder layer that covers a surface of the core portion, and heating the substrate to join the core material to the electrode by the solder bump and the solder layer.Type: ApplicationFiled: June 3, 2021Publication date: December 16, 2021Applicant: SENJU METAL INDUSTRY CO., LTD.Inventors: Takahiro HATTORI, Hiroki SUDO, Hiroshi OKADA, Daisuke SOUMA