Patents by Inventor Hiroki Toyazaki

Hiroki Toyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8525355
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: September 3, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo
  • Publication number: 20120133056
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Application
    Filed: February 8, 2012
    Publication date: May 31, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo
  • Publication number: 20070246842
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 25, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo