Patents by Inventor Hiroki TSUMA

Hiroki TSUMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12615823
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 28, 2026
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Hiroki Tsuma, Yohei Iwahashi, Masashi Uecha
  • Publication number: 20250380448
    Abstract: The semiconductor device includes a semiconductor substrate partitioned into an active region, a peripheral high-breakdown-voltage region, and a boundary region disposed between the active region and the peripheral high-breakdown-voltage region. The semiconductor device further includes a main electrode, an insulating layer disposed in at least a portion of the boundary region and having an end portion facing the active region, a gate wiring disposed above the insulating layer, a gate electrode disposed in the active region, and a gate lead portion connecting the gate electrode and the gate wiring and extending above the end portion of the insulating layer. The boundary region includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer. The second semiconductor layer has a contact portion in contact with the main electrode at a position outside the gate wiring.
    Type: Application
    Filed: May 12, 2025
    Publication date: December 11, 2025
    Inventors: HIROKI TSUMA, TOSHIKI MII, MASATO NOBORIO, JUN SAITO
  • Publication number: 20250336726
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.
    Type: Application
    Filed: July 10, 2025
    Publication date: October 30, 2025
    Inventors: YUJI NAGUMO, MASASHI UECHA, HIROKI TSUMA, TERUAKI KUMAZAWA
  • Patent number: 12424496
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: September 23, 2025
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Yuji Nagumo, Masashi Uecha, Hiroki Tsuma, Teruaki Kumazawa
  • Patent number: 12426329
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: September 23, 2025
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Hiroki Tsuma, Yuji Nagumo, Masashi Uecha, Teruaki Kumazawa
  • Patent number: 12154963
    Abstract: An aluminum alloy film includes an Al—Si—Mg alloy film containing at least 0.9% by weight to 1.1% by weight of Si and 0.1% by weight to 2.3% by weight of Mg, and the Al—Si—Mg alloy film contains Mg silicide crystals in Al crystals. A semiconductor device includes multiple gate trench structures, an interlayer insulating film covering the trench gate structures, an electrode film covering the interlayer insulating film, an insulating layer and a conductive layer covering the electrode film. The electrode film includes the Al—Si—Mg alloy film.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: November 26, 2024
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventor: Hiroki Tsuma
  • Publication number: 20230197519
    Abstract: In a manufacturing method of a semiconductor device, a semiconductor wafer that is made of a semiconductor material harder than silicon and has a first surface and a second surface opposite to each other is prepared, a roughened layer is formed by grinding the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer, the roughened layer is removed after the vertical crack is formed, a rear surface electrode is formed on a rear surface of the semiconductor wafer on which the vertical crack is formed, and after the rear surface electrode is formed, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is cleaved into multiple pieces with the vertical crack as a starting point.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: YUJI NAGUMO, MASASHI UECHA, HIROKI TSUMA, TERUAKI KUMAZAWA
  • Publication number: 20230178497
    Abstract: A semiconductor device includes a semiconductor substrate, an end region, and an active region. The end region is located above the semiconductor substrate, has a frame shape, and has been brought into contact with a blade in a scribing process. The active region is surrounded by the end region and is configured to serve as a path of a main current. The end region has a stress relaxation film on an outermost surface of the end region.
    Type: Application
    Filed: November 15, 2022
    Publication date: June 8, 2023
    Inventors: Masashi UECHA, Yuji NAGUMO, Hiroki TSUMA, Teruaki KUMAZAWA
  • Publication number: 20230154987
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 18, 2023
    Inventors: HIROKI TSUMA, YUJI NAGUMO, MASASHI UECHA, TERUAKI KUMAZAWA
  • Publication number: 20230009078
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 12, 2023
    Inventors: Hiroki TSUMA, Yohei IWAHASHI, Masashi UECHA
  • Publication number: 20220399455
    Abstract: An aluminum alloy film includes an Al—Si—Mg alloy film containing at least 0.9% by weight to 1.1% by weight of Si and 0.1% by weight to 2.3% by weight of Mg, and the Al—Si—Mg alloy film contains Mg silicide crystals in Al crystals. A semiconductor device includes multiple gate trench structures, an interlayer insulating film covering the trench gate structures, an electrode film covering the interlayer insulating film, an insulating layer and a conductive layer covering the electrode film. The electrode film includes the Al—Si—Mg alloy film.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 15, 2022
    Inventor: HIROKI TSUMA
  • Patent number: 10490638
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 26, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi Kuno, Hiroki Tsuma, Satoshi Kuwano, Akitaka Soeno, Toshitaka Kanemaru, Kenta Hashimoto, Noriyuki Kakimoto, Shuji Yoneda
  • Patent number: 10115798
    Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 30, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Akiyama, Hiroki Tsuma, Takashi Kuno, Toshitaka Kanemaru, Kenta Hashimoto
  • Publication number: 20180233571
    Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 16, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki AKIYAMA, Hiroki TSUMA, Takashi KUNO, Toshitaka KANEMARU, Kenta HASHIMOTO
  • Publication number: 20180212028
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 26, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi KUNO, Hiroki TSUMA, Satoshi KUWANO, Akitaka SOENO, Toshitaka KANEMARU, Kenta HASHIMOTO, Noriyuki KAKIMOTO, Shuji YONEDA