Abstract: The present invention is a sealing laminated sheet for an electronic device in which a first sheet and a second sheet 5 are laminated, wherein the first sheet contains an acid-modified polyolefin-based thermoplastic resin, the second sheet 5 has a melting point higher than that of the first sheet, and a peel strength at 25° C. of the second sheet 5 relative to the first sheet is 0.5 to 10.0 N/15 mm. According to the present invention, the production yield of an electronic device can be improved.

Abstract: A photoelectric conversion element module 1 comprises a plurality of photoelectric conversion elements 10 each having a first electrode 15 and a second electrode 25 that oppose each other, and a conductive member 30 electrically connecting the plurality of photoelectric conversion elements 10 to each other; the plurality of photoelectric conversion elements 10 are arranged in planar form such that directions from the first electrodes 15 toward the second electrodes 25 are the same; the first electrode 15 and second electrode 25 have extended portions 15a, 25a respectively which extend to outside a region encompassed by an outer periphery of a sealing member 17; and in adjacent photoelectric conversion elements 10A and 10B, the conductive member 30 connects the extended portion 15a of one of the photoelectric conversion elements 10A and the extended portion 25a of the other photoelectric conversion element 10B; and the extended portion 25a has flexibility.

Abstract: A method of manufacturing a photoelectric conversion element includes: a semiconductor forming step of forming a porous oxide semiconductor layer on a surface of a catalytic layer of a first electrode including a metal plate made of titanium or an alloy including titanium and the catalytic layer, or a surface of a transparent conductor of a second electrode including the transparent conductor; a dye supporting step of supporting a photo-sensitized dye on the porous oxide semiconductor layer; a sealing step of surrounding and sealing the porous oxide semiconductor layer and an electrolyte between the first electrode and the second electrode with a sealing material; and a terminal forming step of forming a terminal on the metal plate. In the terminal forming step, the terminal is formed by applying an ultrasonic wave to a high-melting-point solder while the high-melting-point solder is heated to melt.

Abstract: A method of manufacturing a photoelectric conversion element includes: a first step of forming a porous oxide semiconductor layer on a surface of a catalytic layer of a first electrode including a metal plate made of titanium or a titanium alloy and the catalytic layer, or a surface of a transparent conductor of a second electrode including the transparent conductor; a second step of supporting a photo-sensitized dye on the porous oxide semiconductor layer; a third step of surrounding and sealing the porous oxide semiconductor layer and an electrolyte between the first electrode and the second electrode with a sealing material; and a fourth step of forming a terminal on the metal plate. In the fourth step, the terminal is formed by pressing a metal member including at least one of copper and nickel against the metal plate and applying an ultrasonic wave to the metal member.

Abstract: A photoelectric conversion element module 200 includes a plurality of photoelectric conversion elements 100 and 100, each including a first electrode 10 and a second electrode 20 facing each other, and a conductive member 9 electrically connecting the photoelectric conversion elements 100 to each other. Each of the photoelectric conversion elements 100 is arranged in a planar shape so that a direction from each first electrode 10 to each second electrode 20 is the same. The conductive member 9 is connected to a surface of the first electrode 10 which is opposite to the second electrode 20 in at least one photoelectric conversion element 100 and is connected to a surface of the second electrode 20 which is facing the first electrode 10 in at least one different photoelectric conversion element 100, at a position at which the second electrode 20 does not overlap the first electrode 10.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than the memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the memory circuit section.

Abstract: An electrolyte composition containing an ionic liquid and conductive particles, an electrolyte composition containing an ionic liquid and oxide semiconductor particles and optionally containing conductive particles, and an electrolyte composition containing an ionic liquid and insulating particles are provided. Furthermore, a photoelectric conversion element comprising: a working electrode, the working electrode comprising an electrode substrate and an oxide semiconductor porous film formed on the electrode substrate and sensitized with a dye; a counter electrode disposed opposing the working electrode; and an electrolyte layer made of these electrolyte compositions is provided.

Abstract: The present invention provides a counter electrode that is excellent in photoelectric conversion efficiency and may achieve a photoelectric conversion element where a short circuit between a working electrode and a counter electrode hardly occurs, and a photoelectric conversion element including the counter electrode. The present invention is a counter electrode that includes an intermediate layer made of porous carbon, and an insulating separator that is disposed on one surface of the intermediate layer. The porous carbon includes a plurality of carbon nanotubes.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than the memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the memory circuit section.

Abstract: An electrolyte composition containing an ionic liquid and conductive particles, an electrolyte composition containing an ionic liquid and oxide semiconductor particles and optionally containing conductive particles, and an electrolyte composition containing an ionic liquid and insulating particles are provided. Furthermore, a photoelectric conversion element comprising: a working electrode, the working electrode comprising an electrode substrate and an oxide semiconductor porous film formed on the electrode substrate and sensitized with a dye; a counter electrode disposed opposing the working electrode; and an electrolyte layer made of these electrolyte compositions is provided.

Abstract: A photoelectric conversion element including: (1) a window electrode having a transparent substrate and a semiconductor layer provided on a surface of the transparent substrate, a sensitizing dye being adsorbed on the semiconductor layer; (2) a counter electrode having a substrate and a conductive film, provided on a surface of the substrate, that is arranged so as to face the semiconductor layer of the window electrode, and wherein the counter electrode has carbon nanotubes provided on the substrate surface via the conductive film; and (3) an electrolyte layer disposed at least in a portion between the window electrode and the counter electrode.

Abstract: An electrolyte composition containing an ionic liquid and conductive particles, an electrolyte composition containing an ionic liquid and oxide semiconductor particles and optionally containing conductive particles, and an electrolyte composition containing an ionic liquid and insulating particles are provided. Furthermore, a photoelectric conversion element comprising: a working electrode, the working electrode comprising an electrode substrate and an oxide semiconductor porous film formed on the electrode substrate and sensitized with a dye; a counter electrode disposed opposing the working electrode; and an electrolyte layer made of these electrolyte compositions is provided.

Abstract: A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.

Abstract: A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias gate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ?PD(t)=CD+BD·log(t) is calculated by using constants CD and BD depending on the negative bias voltage, a recovery amount ?PR (t)=CR+BR·log(t) is calculated by using constants CR and BR depending on the bias free voltage, and the deterioration amount (?PD), the recovery amount (?PR) and a basic deterioration amount (XD) are summed.

Abstract: A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias fate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ?PD(t)=CD+BD·log(t) is calculated by using constants CD and BD depending on the negative bias voltage, a recovery amount ?PR(t)=CR+BR·log(t) is calculated by using constants CR and BR depending on the bias free voltage, and the deterioration amount (?PD), the recovery amount (?PR) and a basic deterioration amount (XD) are summed up.

Abstract: An electrolyte composition containing an ionic liquid and conductive particles as main components, an electrolyte composition containing an ionic liquid, and oxide semiconductor particles or oxide semiconductor particles, and conductive particles, and an electrolyte composition containing an ionic liquid and insulating particles are provided. Furthermore, a photoelectric conversion element comprising: a working electrode, the working electrode comprising an electrode substrate and an oxide semiconductor porous film formed on the electrode substrate and sensitized with a dye; a counter electrode disposed opposing the working electrode; and an electrolyte layer made of these electrolyte compositions is provided.

Abstract: A simulator for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, and the method are provided. When a gate voltage of a negative level (a negative bias voltage) “Vg” is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When application of the negative level gate voltage “Vg” is terminated (when applying a bias free voltage), the deteriorated transistor characteristics are recovered.

Abstract: A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.