Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: A method of producing a semiconductor device having a thickness of 90 ?m to 200 ?m and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 ?m to 1.0 ?m and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate.

Abstract: A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. A gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate.