Patents by Inventor Hiroki Yamanaka

Hiroki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140301729
    Abstract: A camera apparatus includes a camera unit that is provided with a camera lens, a camera body that rotatably holds the camera unit, and a rotating mechanism that rotates the camera unit in response to an emergency signal so as to be switched from a first state where the camera lens is stored inside the camera body to a second state where the camera lens is exposed to an outside of the camera body.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 9, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shinichiro OKAMURA, Hiroki YAMANAKA, Tamotsu UCHIDA, Masami ASANUMA
  • Patent number: 8392776
    Abstract: An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: March 5, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Daisuke Ito, Hiroki Yamanaka, Yasuo Sato
  • Publication number: 20100269003
    Abstract: An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 21, 2010
    Inventors: Daisuke ITO, Hiroki Yamanaka, Yasuo Sato
  • Publication number: 20100169727
    Abstract: There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain.
    Type: Application
    Filed: December 26, 2009
    Publication date: July 1, 2010
    Inventors: Daisuke ITO, Hiroki Yamanaka, Koki Tsutsumida