Patents by Inventor Hiroki Yamoto

Hiroki Yamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040181731
    Abstract: A semiconductor test system is disclosed which accepts pincards from multiple vendors, each pincard including a local non-volatile memory in which specific calibration data can be stored. Each pincard in the test system may be capable of performing different types of tests on the DUT. Non-volatile memory on the pincard is used to store pincard calibration data, and loadboard and socket related calibration data may also be stored locally in the non-volatile memory of each pincard for use in compensating for signal degradation. Calibration data related to pincard slots (i.e. slot-to-slot skew) may be stored in nonvolatile memory on a test system backplane and used to calibrate slot-to-slot skew of the pincard. Local non-volatile memory may also be used to store commands, data, and error information being generated in or transferred between modules, site controllers and the system controller, so that this information does not need to be regenerated if a system error should occur.
    Type: Application
    Filed: January 16, 2004
    Publication date: September 16, 2004
    Applicant: ADVANTEST CORPORATION
    Inventors: Rochit Rajsuman, Robert Sauer, Hiroki Yamoto
  • Patent number: 6747447
    Abstract: The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: June 8, 2004
    Assignee: Advantest Corporation
    Inventors: Niels Markert, Anthony Le, Robert Sauer, Rochit Rajsuman, Hiroki Yamoto
  • Publication number: 20040056675
    Abstract: The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Applicant: ADVANTEST CORPORATION
    Inventors: Niels Markert, Anthony Le, Robert Sauer, Rochit Rajsuman, Hiroki Yamoto
  • Patent number: 6710590
    Abstract: The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 23, 2004
    Assignee: Advantest Corporation
    Inventors: Niels Markert, Anthony Le, Hiroki Yamoto, Robert Sauer
  • Publication number: 20030110427
    Abstract: A semiconductor test system is disclosed which accepts pincards from multiple vendors, each pincard including a local non-volatile memory in which specific calibration data can be stored. Each pincard in the test system may be capable of performing different types of tests on the DUT. Non-volatile memory on the pincard is used to store pincard calibration data, and loadboard and socket related calibration data may also be stored locally in the non-volatile memory of each pincard for use in compensating for signal degradation. Calibration data related to pincard slots (i.e. slot-to-slot skew) may be stored in nonvolatile memory on a test system backplane and used to calibrate slot-to-slot skew of the pincard.
    Type: Application
    Filed: January 10, 2003
    Publication date: June 12, 2003
    Applicant: ADVANTEST CORPORATION
    Inventors: Rochit Rajsuman, Robert Sauer, James Alan Turnquist, Hiroki Yamoto, Shigeru Sugamori