Patents by Inventor Hiroki Yano
Hiroki Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7397765Abstract: In one embodiment, a bandwidth monitoring device comprises a packet receiving circuit configured to receive packets; a counter configured to count a total packet length by adding up inputted packet lengths including a packet length of a next input packet and subtracting outputted packet lengths to produce a counted value; a timer configured to time a packet receiving time; a memory configured to store a number of packet receiving times and a number of counted values counted by the counter which correspond to the packet receiving times, respectively; a counter rate-of-change calculating portion configured to calculate a change rate by a first counted value corresponding to an oldest packet receiving time stored in the memory representing an oldest time at which a packet was received and a second counted value corresponding to a latest packet receiving time stored in the memory representing a latest time at which a packet was received; and a determining portion configured to decide whether the next input packetType: GrantFiled: January 30, 2004Date of Patent: July 8, 2008Assignee: Hitachi, Ltd.Inventors: Takeshi Aimoto, Nobuhito Matsuyama, Kazuo Sugai, Hiroki Yano, Yoshihiko Sakata, Shinichi Akahane, Yuichi Ishikawa
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Patent number: 7379454Abstract: A packet routing apparatus has a routing information table comprised of a plurality of sub-tables. Each sub-table includes an entry of a first format indicative of routing information, and at least one of the sub-tables includes, in addition to the entry of the first format, an entry of a second format for designating another sub-table to be referred to. A routing processor of the packet routing apparatus refers to a sub-table designated by an input line interface. As a result, when the entry of the second format is retrieved, the routing processor executes routing of an input packet and header conversion by referring to another sub-table designated by the entry.Type: GrantFiled: August 5, 2002Date of Patent: May 27, 2008Assignee: Hitachi, Ltd.Inventors: Nobuo Ogasawara, Kenichi Sakamoto, Shinichi Akahane, Hiroki Yano, Tomohiro Baba
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Publication number: 20080049778Abstract: Packets are relayed using a network relay device including a plurality of interface units. Each of the interface units includes one or more physical ports for connection to a line, and a bandwidth controller configured to control transmission bandwidth for packets received by the physical ports. Furthermore, a single specific physical port is selected as the output physical port from the distributed-control logical port based on output port group information unique to the output port group including the distributed-control logical port.Type: ApplicationFiled: July 31, 2007Publication date: February 28, 2008Inventors: Hiroki Yano, Kazuo Sugai, Shinichi Akahane, Yoshinori Hachiya
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Publication number: 20080052487Abstract: A network switching device includes multiple ports, multiple switching processors, and a table manager. The switching processors respectively have an address table, a output port specification module, an update requirement determination module, and a table update module. The output port specification module refers to a destination address in received data and the address table and specifies a output port for sending the data among the multiple ports. The update requirement determination module determines requirement for update of the address table with regard to a source address in the data. The table manager has an update detail acquisition module and an update request module. Upon determination of the requirement for update of the address table, the update detail acquisition module obtains an update detail of the address table from one of the switching processors. The update request module sends an update request to the switching processors, based on the update detail.Type: ApplicationFiled: July 31, 2007Publication date: February 28, 2008Inventors: Shinichi Akahane, Mitsuru Nagasaka, Hiroki Yano, Yutaka Takagi
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Publication number: 20080037544Abstract: Computing process with a computational expression is executed using seed information including at least one of destination information and source information associated with a received packet. It is preferable to select a physical port for transmission of the received packet based on the result of the computation. It is also preferable to select a port group for transmission of the received packet based on the result of the computation. Here, the computational expression is capable of being modified. Meanwhile, the physical port for transmission of the received packet is selected from a plurality of candidate ports among the plurality of physical ports. The port group for transmission of the received packet is selected from among a plurality of port groups including a mutually different candidate port.Type: ApplicationFiled: July 31, 2007Publication date: February 14, 2008Inventors: Hiroki YANO, Kazuo SUGAI, Shinichi AKAHANE, Takao NARA
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Patent number: 7292532Abstract: A traffic shaping apparatus calculates a minimum transmission interval, an allowed transmission frame rate of a user frame, and a reference transmission interval for each user according to a minimum transmission frame rate and a peak transmission frame rate specified for each user. The traffic shaping apparatus also calculates a first estimated transmission time according to the reference transmission interval, and a second estimated transmission time according to the minimum transmission interval for each user. The traffic shaping apparatus determines the user having the earliest first estimated transmission time, and determines according to the second estimated transmission time of the user whether a user frame is to be transmitted.Type: GrantFiled: February 24, 2004Date of Patent: November 6, 2007Assignee: Hitachi, Ltd.Inventors: Yoshihiko Sakata, Atsushi Anzai, Takeshi Aimoto, Hiroki Yano, Kaoru Okano
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Publication number: 20070133531Abstract: The present invention provides a technology for processing packets, such as VoIP packets, with priority. A priority-designating unit designates priority information based on header information. A pointer searching unit refers to a pointer table to obtain pointer information corresponding to a destination address. A sorting unit sorts the pointer information into a high-priority queue and a low-priority queue according to the priority information. A next queue holds pointer information obtained from a destination information table. A scheduler extracts and outputs the pointer information from each queue in the following order of priority: the next queue, a high-priority queue, and a low-priority queue.Type: ApplicationFiled: March 24, 2006Publication date: June 14, 2007Inventors: Yasuhiro Kodama, Kazuo Sugai, Shinichi Akahane, Hiroki Yano, Kaoru Okano, Naoya Kumita
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Publication number: 20040208123Abstract: A traffic shaping apparatus calculates a minimum transmission interval, an allowed transmission frame rate of a user frame, and a reference transmission interval for each user according to a minimum transmission frame rate and a peak transmission frame rate specified for each user. The traffic shaping apparatus also calculates a first estimated transmission time according to the reference transmission interval, and a second estimated transmission time according to the minimum transmission interval for each user. The traffic shaping apparatus determines the user having the earliest first estimated transmission time, and determines according to the second estimated transmission time of the user whether a user frame is to be transmitted.Type: ApplicationFiled: February 24, 2004Publication date: October 21, 2004Inventors: Yoshihiko Sakata, Atsushi Anzai, Takeshi Aimoto, Hiroki Yano, Kaoru Okano
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Publication number: 20040184444Abstract: In one embodiment, a bandwidth monitoring device comprises a packet receiving circuit configured to receive packets; a counter configured to count a total packet length by adding up inputted packet lengths including a packet length of a next input packet and subtracting outputted packet lengths to produce a counted value; a timer configured to time a packet receiving time; a memory configured to store a number of packet receiving times and a number of counted values counted by the counter which correspond to the packet receiving times, respectively; a counter rate-of-change calculating portion configured to calculate a change rate by a first counted value corresponding to an oldest packet receiving time stored in the memory representing an oldest time at which a packet was received and a second counted value corresponding to a latest packet receiving time stored in the memory representing a latest time at which a packet was received; and a determining portion configured to decide whether the next input packetType: ApplicationFiled: January 30, 2004Publication date: September 23, 2004Applicant: HITACHI, LTD.Inventors: Takeshi Aimoto, Nobuhito Matsuyama, Kazuo Sugai, Hiroki Yano, Yoshihiko Sakata, Shinichi Akahane, Yuichi Ishikawa
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Publication number: 20030026260Abstract: A packet routing apparatus has a routing information table comprised of a plurality of sub-tables. Each sub-table includes an entry of a first format indicative of routing information, and at least one of the sub-tables includes, in addition to the entry of the first format, an entry of a second format for designating another sub-table to be referred to. A routing processor of the packet routing apparatus refers to a sub-table designated by an input line interface. As a result, when the entry of the second format is retrieved, the routing processor executes routing of an input packet and header conversion by referring to another sub-table designated by the entry.Type: ApplicationFiled: August 5, 2002Publication date: February 6, 2003Inventors: Nobuo Ogasawara, Kenichi Sakamoto, Shinichi Akahane, Hiroki Yano, Tomohiro Baba
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Patent number: 5254233Abstract: A monopolar ion exchange membrane electrolytic cell assembly comprising a plurality of unit electrolytic cells connected electritically in parallel to one another, each formed by clamping an anode compartment frame and a cathode compartment frame with an ion exchange membrane interposed therebetween, the anode and cathode compartment frames each having a feeding and discharging system for an electrolyte and a discharging system for generated gas, wherein:(a) an anode is made of a foraminous plate fixed to the anode compartment frame so that it is close to or in contact with the ion exchange membrane, and electricity is supplied to the foraminous plate via power supply rods and/or power supply ribs from a power source located outside the cell,(b) a cathode is made of flexible foraminous metal plate having good conductivity with an electric resistance at 20.degree. C. of not higher than 10 .mu..OMEGA..Type: GrantFiled: July 10, 1992Date of Patent: October 19, 1993Assignee: Asahi Glass Company Ltd.Inventors: Makoto Nakao, Hidenori Shibata, Takeo Aikawa, Takahiro Uchibori, Hiroki Yano
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Patent number: 5221452Abstract: A monopolar ion exchange membrane electrolytic cell assembly comprising a plurality of unit electrolytic cells connected electritically in parallel to one another, each formed by clamping an anode compartment frame and a cathode compartment frame with an ion exchange membrane interposed therebetween, the anode and cathode compartment frames each having a feeding and discharging system for an electrolyte and a discharging system for generated gas, wherein:(a) an anode is made of a foraminous plate fixed to the anode compartment frame so that it is close to or in contact with the ion exchange membrane, and electricity is supplied to the foraminous plate via power supply rods and/or power supply ribs from a power source located outside the cell,(b) a cathode is made of flexible foraminous metal plate having good conductivity with an electric resistance at 20.degree. C. of not higher than 10 .mu..OMEGA..Type: GrantFiled: February 12, 1991Date of Patent: June 22, 1993Assignee: Asahi Glass Company Ltd.Inventors: Makoto Nakao, Hidenori Shibata, Takeo Aikawa, Takahiro Uchibori, Hiroki Yano