Patents by Inventor Hiroko Aikawa

Hiroko Aikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7155626
    Abstract: A data processor which may prevent data processing being executed from being analyzed based on the power consumption has been disclosed. A data processor (100) may include clock generating circuit (101), a random number generating circuit (102), a clock thinning-out circuit (103), and circuit resources (105 to 109). A clock signal (CLOCK A) may be thinned out by clock thinning out circuit (103) in correspondence to a random number generated by a random number generating circuit (102) to provide a clock signal (CLOCK C) to circuit resources (105 to 109). In this way, correct analysis of data processing being executed based on monitoring power consumption may be prevented.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 26, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Hiroko Aikawa
  • Publication number: 20030145243
    Abstract: A data processor which may prevent data processing being executed from being analyzed based on the power consumption has been disclosed. A data processor (100) may include clock generating circuit (101), a random number generating circuit (102), a clock thinning-out circuit (103), and circuit resources (105 to 109). A clock signal (CLOCK A) may be thinned out by clock thinning out circuit (103) in correspondence to a random number generated by a random number generating circuit (102) to provide a clock signal (CLOCK C) to circuit resources (105 to 109). In this way, correct analysis of data processing being executed based on monitoring power consumption may be prevented.
    Type: Application
    Filed: January 24, 2003
    Publication date: July 31, 2003
    Inventor: Hiroko Aikawa
  • Patent number: 6046692
    Abstract: A microprocessor which can be used as a microprocessor with 8-bit A/D converter or 10-bit A/D converter is disclosed. Voltage comparator 2 compares the analog input signal AIN level with the reference voltage VREF, and then generates the comparative signal CP. The comparative signal CP is supplied to the serial conversion register 3 in order and is stored as the converted data DC. The upper 8 bits of the converted data DC stored in the serial conversion register 3 are supplied to the conversion result register 4A, and the lower 2 bits are supplied to the conversion result register 5A. In this way, in the case where this microprocessor is used as an microprocessor with a built-in 8-bit A/D converter, the microprocessor only ignores the contents of the conversion result register 5A.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: April 4, 2000
    Assignee: NEC Corporation
    Inventors: Kiyomi Yamashiro, Hiroko Aikawa