Patents by Inventor Hiroko Oka

Hiroko Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7619620
    Abstract: A test circuit for detecting an output signal from a driving circuit includes a judging circuit which outputs a detection signal when the output signal output from the driving circuit has one polarity, but does not output the detection signal when the output signal has the other polarity, and an amplifying circuit which amplifies the signal from the judging circuit.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: November 17, 2009
    Assignee: Epson Imaging Devices Corporation
    Inventors: Shin Fujita, Hiroko Oka
  • Publication number: 20080171356
    Abstract: A soybean protein that without any soybean odor and nasty aftertastes, such as acerbity and astringency, is refreshing and ensures excellent flavor, and that when used in a protein beverage, etc., excels in powder dispersion and dissolution at the time of dissolving operation and is free of roughness thereof, realizing excellent throat feeling. There is provided a process for producing a soybean protein, characterized by adding an Mg compound to a soybean protein slurry or solution, heating the thus neutralized solution and adding a protease thereto, thereby carrying out hydrolysis of the protein.
    Type: Application
    Filed: January 27, 2006
    Publication date: July 17, 2008
    Inventors: Yasushi Nakamura, Hiroko Oka, Tetsuo Sakata
  • Patent number: 7282952
    Abstract: A level shift circuit includes a capacitor element that has one terminal to which a logic input signal having a first logic amplitude is input; a logic output circuit that includes a first logic inverting circuit having a first logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element; and a second logic inverting circuit having a second logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element, and that inverts a logic output signal having a second logic amplitude when output polarities of the first logic inverting circuit and the second logic inverting circuit coincide with each other; and a third logic inverting circuit whose input and output terminals are connected to the other terminal of the capacitor element and that has a third logic inversion level with respect to the input terminal thereof connected to the other terminal of the capacitor element.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: October 16, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Hiroko Oka
  • Publication number: 20060279313
    Abstract: A test circuit for detecting an output signal from a driving circuit includes a judging circuit which outputs a detection signal when the output signal output from the driving circuit has one polarity, but does not output the detection signal when the output signal has the other polarity, and an amplifying circuit which amplifies the signal from the judging circuit.
    Type: Application
    Filed: May 11, 2006
    Publication date: December 14, 2006
    Applicant: Sanyo Epson Imaging Devices Corp.
    Inventors: Shin Fujita, Hiroko Oka
  • Publication number: 20060169909
    Abstract: A level shift circuit includes a capacitor element that has one terminal to which a logic input signal having a first logic amplitude is input; a logic output circuit that includes a first logic inverting circuit having a first logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element; and a second logic inverting circuit having a second logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element, and that inverts a logic output signal having a second logic amplitude when output polarities of the first logic inverting circuit and the second logic inverting circuit coincide with each other; and a third logic inverting circuit whose input and output terminals are connected to the other terminal of the capacitor element and that has a third logic inversion level with respect to the input terminal thereof connected to the other terminal of the capacitor element.
    Type: Application
    Filed: January 11, 2006
    Publication date: August 3, 2006
    Inventor: Hiroko Oka
  • Patent number: 6294547
    Abstract: A novel naphthyridine compound represented by the general formula (1): wherein R1, R2 and R3 are independently a hydrogen atom, a lower alkyl group or the like, or R1 and R2, or R2 and R3, when taken together, form a cyclic group; each of X and Y is a methylene or ethylene group; Z is a phenyl group, a substituted phenyl group or the like; A is a hydrogen atom, a lower alkyl group or the like; and G is an acyl group, shows antagonism for tachykinin receptors and is useful as a prophylactic or therapeutic agent for diseases for which the tachykinin receptors are considered to be responsible. A specific example of such a compound is 2-[(−)-4-(N-benzoyl-N-methyl)amino-3-(3,4-dichlorophenyl)butyl]-10-acetylamino-1,2,3,4-tetrahydro-benzo[b][1,6]naphthyridine.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: September 25, 2001
    Assignee: Nippon Kayaku Kabushiki Kaisha
    Inventors: Hiroko Oka, Masashi Iida, Yoshitaka Sato, Maki Honda