Patents by Inventor Hiroko Sehata

Hiroko Sehata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230104638
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 6, 2023
    Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
  • Publication number: 20230036779
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: Hideo TANABE, Masaru TAKABATAKE, Toshiki KANEKO, Atsushi HASEGAWA, Hiroko SEHATA
  • Patent number: 11536999
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 27, 2022
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
  • Patent number: 11532371
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: December 20, 2022
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20210366564
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
  • Patent number: 11114177
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 7, 2021
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20210181569
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 17, 2021
    Inventors: Hideo TANABE, Masaru TAKABATAKE, Toshiki KANEKO, Atsushi HASEGAWA, Hiroko SEHATA
  • Patent number: 10962815
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 30, 2021
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
  • Publication number: 20200321068
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
  • Patent number: 10726933
    Abstract: A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 28, 2020
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20200150484
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Hideo TANABE, Masaru TAKABATAKE, Toshiki KANEKO, Atsushi HASEGAWA, Hiroko SEHATA
  • Patent number: 10564459
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 18, 2020
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
  • Publication number: 20190156905
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
  • Patent number: 10210945
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 19, 2019
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20190049775
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Hideo TANABE, Masaru TAKABATAKE, Toshiki KANEKO, Atsushi HASEGAWA, Hiroko SEHATA
  • Patent number: 10133103
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 20, 2018
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
  • Publication number: 20180114584
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Application
    Filed: December 20, 2017
    Publication date: April 26, 2018
    Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
  • Patent number: 9881691
    Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 30, 2018
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Takahiro Ochiai, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
  • Publication number: 20170343851
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Hideo TANABE, Masaru TAKABATAKE, Toshiki KANEKO, Atsushi HASEGAWA, Hiroko SEHATA
  • Patent number: 9766489
    Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 19, 2017
    Assignees: JAPAN DISPLAY INC., PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata