Abstract: Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at a packaging design stage, and shortening the time required for designing the integrated circuit. The present invention is able to accurately estimate the wiring length between the modules and the wiring congestion in the modules at the stage of implementing the logical design of the integrated circuit, and reflect the logical design result of the integrated circuit in the packaging design of the integrated circuit.

Abstract: This invention proposes a storage controller and its power saving methods capable of significantly saving power consumption. The storage controller of this invention is connected to host terminals and storage devices, controls data storage in the storage devices, and includes a microprocessor including one or more ports and at the same time controlling the entire relevant device via the relevant ports, and multiple types of components including one or more ports and at the same time configuring data paths between the host terminals and the storage devices via the relevant ports, and the microprocessor detects, among the ports of the relevant microprocessor or the component, those not connected to any of the host terminals, any of the storage devices, or any of the ports of the other components as unconnected ports, and stops the power supply to the detected unconnected ports.

Abstract: Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at a packaging design stage, and shortening the time required for designing the integrated circuit. The present invention is able to accurately estimate the wiring length between the modules and the wiring congestion in the modules at the stage of implementing the logical design of the integrated circuit, and reflect the logical design result of the integrated circuit in the packaging design of the integrated circuit.