Patents by Inventor Hiromasa Nakagawa
Hiromasa Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240078717Abstract: The information processing method includes segment extraction processing and adjustment processing. In the segment extraction processing, a segment corresponding to a label associated with an effect is extracted from a video of a camera (20). In the adjustment processing, an application position of the effect is adjusted according to a change in a posture of the camera (20), which posture is detected by utilization of information including acceleration data, in such a manner that the application position of the effect is not deviated from the extracted segment.Type: ApplicationFiled: January 27, 2022Publication date: March 7, 2024Inventors: Hiromasa Doi, Takaaki Nakagawa, Guangyu Wang
-
Patent number: 11493007Abstract: A cover covering an engine and an intake duct for introducing fresh air outside an engine room into a combustion chamber of the engine are provided in the engine room. The cover includes a top face cover portion covering the engine from above, and a side face cover portion covering the engine from the lateral side. The intake duct is disposed so as to be continuous to a side edge of the side face cover portion such that the intake duct covers the engine from the lateral side together with the side face cover portion.Type: GrantFiled: September 3, 2019Date of Patent: November 8, 2022Assignee: Mazda Motor CorporationInventors: Shin Kodama, Kenji Sugasaki, Hiromasa Nakagawa
-
Patent number: 11371474Abstract: A heat storage cover is provided in an engine room. The heat storage cover covers an engine from above and surrounds the periphery of an upper portion of the engine to internally store, through the medium of air, heat dissipated from the engine and block upward heat dissipation. The engine includes an air inlet for introducing, into a combustion chamber, high temperature air obtained by the heat storage cover blocking the upward heat dissipation.Type: GrantFiled: September 3, 2019Date of Patent: June 28, 2022Assignee: Mazda Motor CorporationInventors: Shin Kodama, Kenji Sugasaki, Hiromasa Nakagawa
-
Patent number: 11181054Abstract: An intake-air temperature controlling device for an engine is provided, which includes an engine body, an intake passage, an air intake part, an intake air temperature adjuster configured to adjust air temperature taken in through the air intake part to the passage, and a controller. An operating range in which the CI combustion is performed has a lean operating range in which A/F of mixture gas formed inside the cylinder, or G/F that is a relationship between the total weight G of gas inside the cylinder and a weight F of fuel fed to the cylinder is relatively low, and a rich operating range in which the A/F or G/F is relatively high. When the engine is in the lean operating range, the controller outputs a control signal to the intake air temperature adjuster so that the air temperature is increased, as compared in the rich operating range.Type: GrantFiled: November 5, 2019Date of Patent: November 23, 2021Assignee: Mazda Motor CorporationInventors: Shinichi Hikitani, Hajime Umehara, Naoki Nagano, Kenji Sugasaki, Shin Kodama, Hiromasa Nakagawa, Tomokuni Kusunoki, Taiga Kamiji, Masanobu Koutoku, Toshinori Ueno, Katsuya Murakami
-
Publication number: 20210340940Abstract: A cover covering an engine and an intake duct for introducing fresh air outside an engine room into a combustion chamber of the engine are provided in the engine room. The cover includes a top face cover portion covering the engine from above, and a side face cover portion covering the engine from the lateral side. The intake duct is disposed so as to be continuous to a side edge of the side face cover portion such that the intake duct covers the engine from the lateral side together with the side face cover portion.Type: ApplicationFiled: September 3, 2019Publication date: November 4, 2021Inventors: Shin KODAMA, Kenji SUGASAKI, Hiromasa NAKAGAWA
-
Publication number: 20210254585Abstract: A heat storage cover is provided in an engine room. The heat storage cover covers an engine from above and surrounds the periphery of an upper portion of the engine to internally store, through the medium of air, heat dissipated from the engine and block upward heat dissipation. The engine includes an air inlet for introducing, into a combustion chamber, high temperature air obtained by the heat storage cover blocking the upward heat dissipation.Type: ApplicationFiled: September 3, 2019Publication date: August 19, 2021Inventors: Shin KODAMA, Kenji SUGASAKI, Hiromasa NAKAGAWA
-
Publication number: 20200208579Abstract: An intake-air temperature controlling device for an engine is provided, which includes an engine body, an intake passage, an air intake part, an intake air temperature adjuster configured to adjust air temperature taken in through the air intake part to the passage, and a controller. An operating range in which the CI combustion is performed has a lean operating range in which A/F of mixture gas formed inside the cylinder, or G/F that is a relationship between the total weight G of gas inside the cylinder and a weight F of fuel fed to the cylinder is relatively low, and a rich operating range in which the A/F or G/F is relatively high. When the engine is in the lean operating range, the controller outputs a control signal to the intake air temperature adjuster so that the air temperature is increased, as compared in the rich operating range.Type: ApplicationFiled: November 5, 2019Publication date: July 2, 2020Inventors: Shinichi Hikitani, Hajime Umehara, Naoki Nagano, Kenji Sugasaki, Shin Kodama, Hiromasa Nakagawa, Tomokuni Kusunoki, Taiga Kamiji, Masanobu Koutoku, Toshinori Ueno, Katsuya Murakami
-
Patent number: 5638537Abstract: A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.Type: GrantFiled: July 25, 1996Date of Patent: June 10, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Yamada, Masayuki Hata, Hiromasa Nakagawa, Koichi Nishida
-
Patent number: 5544341Abstract: A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.Type: GrantFiled: May 31, 1995Date of Patent: August 6, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromasa Nakagawa, Akira Yamada, Masayuki Hata
-
Patent number: 5535359Abstract: A computer system is provided with a plurality of cache memories. Each cache memory stores data corresponding to part of main memory address space without overlapping with each other, thereby enabling capacity of the cache memory to be increased with ease. An address mask register is used to allocate the portion of main memory address space stored in each cache.Type: GrantFiled: February 13, 1995Date of Patent: July 9, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masayuki Hata, Hiromasa Nakagawa, Tatsuo Yamada
-
Patent number: 5459852Abstract: A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU read-access request for a single data. The data of the address designated by the CPU is read simultaneously into the CPU and cache in parallel from the memory system. After the CPU completes this read-access, the cache is then adapted to continue to read the rest of the multiple data transferred in the block transfer mode. During this time, the CPU does not newly assert an address signal, a bus control signal, and the like but continues to execute its internal processing, such as pipeline processing.Type: GrantFiled: January 23, 1995Date of Patent: October 17, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromasa Nakagawa, Akira Yamada, Masayuki Hata
-
Patent number: 5454088Abstract: A microprogram control device controls a data path section provided in a CPU, which uses a microcode stored in a microprogram memory by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal to access the microprogram memory, from the output of the instruction register. The address generator uses a first address decoder for decoding the type of the instruction from a particular bit in the instruction code and a second address decoder for decoding the addressing mode of the instruction from another particular bit of the instruction code. A third address decoder is included for designating the timing for accessing the microprogram memory at each cycle of the instruction.Type: GrantFiled: May 17, 1993Date of Patent: September 26, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromasa Nakagawa, Tsunenori Umeki
-
Patent number: 4908690Abstract: A semiconductor integrated circuit device includes a semiconductor substrate and a wiring layer formed on the substrate. An output buffer transistor is provided with its gate formed along the direction of the wiring. The resulting device has improved area efficiency and is less susceptible to wiring element slide without requiring slits to be formed in the wiring structure--and thus also has lower current density.Type: GrantFiled: October 13, 1987Date of Patent: March 13, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masayuki Hata, Hiromasa Nakagawa
-
Patent number: 4899066Abstract: A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.Type: GrantFiled: April 7, 1986Date of Patent: February 6, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masatoshi Aikawa, Hiromasa Nakagawa, Tsunenori Umeki
-
Patent number: 4807176Abstract: A Manchester type carry propagation circuit of this invention has a precharge clock signal (24) applied to the gate of an NMOS transistor (23) having a high threshold, to precharge a carry signal line (22) to an intermediate potential. When a carry signal (27) of the preceding stage attains to the "H" level, a transistor (26) turns on to transmit the potential of the carry signal line (22) to the succeeding stage, and when a carry propagation signal (37) attains to the "H" level, a transistor (36) turns on to propagate a carry of the preceding stage to the carry signal line (22). Then, the intermediate level of the carry signal line (22) is pulled up to the level of the source potential (21) by a pull-up circuit (30). Consequently, the level of the carry signal line (22) can be propagated to the succeeding stage at high speed.Type: GrantFiled: March 10, 1986Date of Patent: February 21, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Yamada, Toyohiko Yoshida, Hiromasa Nakagawa