Patents by Inventor Hiromasa Yamaoka

Hiromasa Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5796936
    Abstract: A distributed control system includes a plurality of controllers each composed of a plurality of processors and being coupled through a network. Each controller includes a scheduler for measuring a load; internal backup means for controlling which controller bears the load; backup request means for requesting another controller to bear the load; and backup accept means for answering to a request for bearing the load from another controller in accordance with the load of the requesting controller. Thus, the load which cannot be executed by one controller can be distributed and executed by other controllers in accordance with their loads.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: August 18, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuru Watabe, Hiromasa Yamaoka
  • Patent number: 5682466
    Abstract: An information processing apparatus, which is easy to design and has functions of high speed processing, learning, and so on, includes a plurality of memories for storing sets of previously known input data (called response pattern data) and correct output data corresponding thereto; a comparator for providing input data supplied in actual operations to the plurality of sets and comparing the input data with the response pattern data in each set; an evaluation unit for evaluating the distance (degree of similarity) between the input data and the response pattern data; and a generator for generating final outputs by composing the evaluation result for each set and the output data in that set, for example, using a method which calculates weighted average values based on the evaluated distances.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: October 28, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Maeda, Motohisa Funabashi, Hiromasa Yamaoka, Nobuyuki Fujikura, Mikio Yoda, Mitsuo Yanagi
  • Patent number: 5638492
    Abstract: An information processing apparatus is capable of achieving high-level functions such as high-speed processing and learning without requiring a complex algorithm based on, for example, knowledge processing. A plurality of sets of known input data and correct output data corresponding thereto are beforehand stored. The stored input data is called response pattern data. Data actually inputted in the system operation is supplied to the plural sets of data. For each set of data, the input data is compared with the response pattern data to evaluate a distance (degree of similarity) therebetween. Results of evaluations for the respective sets of data are combined with the associated output data, for example, according to weighted average values on the basis of the evaluated distance, thereby generating final outputs.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: June 10, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Maeda, Motohisa Funabashi, Hiromasa Yamaoka, Nobuyuki Fujikura, Mikio Yoda, Mitsuo Yanagi, Toshihide Ichimori
  • Patent number: 5504673
    Abstract: A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: April 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okamoto, Hiromasa Yamaoka, Kazuhiko Shimoyama
  • Patent number: 5410470
    Abstract: A process control method and a process control apparatus using a fuzzy control with reducing rules and membership functions. The process control apparatus for determining a manipulating variable of a controlled object, includes an input/output unit for inputting a present value of a controlled variable and for outputting the determined manipulating variable, a predicting unit having a simulator of a controlled object, for calculating a control variable after a predetermined time has passed, assuming now that a present value of the manipulating variable is continued, and a fuzzy controlling unit for inferring a manipulating variable at a present time by inputting a deviation value between a preset set-point value and a predicted value. The simulator simulates the controlled object as dead time and a first order delay. Since only the predicted value of the controlled variable is employed as the input of the fuzzy control, fuzzy inference can be simplified and noise resistance can be improved.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Yamaoka, Mitsuaki Kobayashi, Yasuhiro Tennichi, Tadayoshi Saito
  • Patent number: 5237687
    Abstract: A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.
    Type: Grant
    Filed: August 22, 1985
    Date of Patent: August 17, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okamoto, Hiromasa Yamaoka, Kazuhiko Shimoyama
  • Patent number: 5090029
    Abstract: A method and apparatus for transmission of data among computers or peripherals along a loop transmission line includes a master system which provides signals along the transmission line for establishing a series of data frames of equivalent length. Each data frame is assigned a frame number, and is allotted a preselected amount of available space for placement of data. Subsequent computers or peripherals are preprogramed with a series of frame numbers which identify those data frames into which they may write data, or from which data is to be read. The allotment of preselected frame numbers for placement and reception of data by the respective devices provides for equivalent sharing of the available data transmission capability of the loop transmission system.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: February 18, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Toshifumi Yamamoto, Mitsuro Takakura, Hiromasa Yamaoka, Masakazu Okada
  • Patent number: 4694419
    Abstract: A programmable controller for controlling a plant on the basis of a stored program includes a processing unit for reading out an instruction from a program memory to process the instruction. In the processing unit, it is determined whether the instruction read out from the memory is an instruction taking a register-modified addressing mode or an instruction taking a direct addressing mode. When the read-out instruction is an instruction taking the direct addressing mode, a plant is directly addressed by the address part of the instruction. Then, an arithmetic operation is performed using the state information which is read out from the plant thus addressed, or plant control information is sent from the processing unit to the plant thus addressed.
    Type: Grant
    Filed: October 5, 1984
    Date of Patent: September 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okamoto, Kazuhiko Shimoyama, Hiromasa Yamaoka, Mitsuro Takakura
  • Patent number: 4688193
    Abstract: A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: August 18, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Yamaoka, Tadashi Okamoto, Yuzaburo Iwasa, Kouichi Kimura
  • Patent number: 4628436
    Abstract: A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory for simplifying the programming, while the operands are stored in memories each incorporated in each of the processors adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors in parallel with one another. Overall processing speed is made thus significantly high.
    Type: Grant
    Filed: February 22, 1984
    Date of Patent: December 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okamoto, Hiromasa Yamaoka
  • Patent number: 4494113
    Abstract: Method and apparatus for controlling collision in a system having a common unit shared by a plurality of devices are disclosed. More particularly, method and apparatus for controlling priority collision in a system where a computer is shared by a plurality of terminal devices or a memory unit is shared by a plurality of computers are disclosed. Continued time period of non-access to the common unit by any of the plurality of devices is measured in each of the plurality of devices, and when the measured time period coincides with one of preset time periods inherently assigned to the respective devices, the associated one of the plurality of devices is permitted to access to the common unit on the condition that the common unit is not busy and that one device issues an access request to the common unit. In addition to ordinary access request to the common unit, a priority interruption access request may be issued.
    Type: Grant
    Filed: March 10, 1982
    Date of Patent: January 15, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Yamaoka, Yuzaburo Iwasa, Kazuhisa Matunaga