Abstract: A data network management system includes a data network management apparatus; and plural data processing apparatuses installed in an installation area and configured to transmit data to the data network management apparatus. The plural data processing apparatuses transmit identification information thereof together with the processed data to the data network management apparatus. The data network management apparatus determines based on identification information of data processing apparatuses that have completed a given authentication test among the plural data processing apparatuses and the identification information obtained from the plural data processing apparatuses installed in the installation area, a first data processing apparatus from which the data is to be obtained among the plural data processing apparatuses.

Abstract: A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.

Abstract: A multi-core processor system includes a core configured to determine whether a task to be synchronized with a given task is present; identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is present, a core to which no non-synchronous task that is not synchronized with another task has been assigned, and identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is not present, a core to which no synchronous task to be synchronized with another task has been assigned; and send to the identified core, an instruction to start the given task.

Abstract: A communications node includes a first transmitting circuit configured to transmit to plural communications nodes, a confirmation signal for confirming whether response is possible; a receiving circuit configured to receive from first communications nodes capable of responding among the plural communications nodes, a response signal for the transmitted confirmation signal; a selecting circuit configured to select from among the first communications nodes and based on reception strength of the received response signal, a second communications node to which execution of data processing is requested by the communications node; a strength calculating circuit configured to calculate based on the reception strength of the response signal from the selected second communications node, a transmission strength to the second communications node; and a second transmitting circuit configured to transmit to the second communications node and based on the calculated transmission strength, a request signal requesting executi

Abstract: A communications method includes transmitting a sensor data collection request to a second network that includes a group of nodes having sensors, the transmitting being performed by a first communications apparatus of plural of communications apparatuses configured to communicate through a first network; and transmitting reception information to the first communications apparatus via the first network, when sensor data is received that is transferred by multihop communication among nodes in the second network and corresponds to the sensor data collection request, the reception information indicating reception of the sensor data, and the transmitting of the reception information being performed by a second communications apparatus of the plural communications apparatuses.

Abstract: A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.

Abstract: In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result.

Abstract: A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change.

Abstract: A data collection method of a system that transmits and receives data by respective communications apparatuses among plural communications apparatuses performing multihop communication, includes suspending transmission of data obtained from a second sensor, a communications apparatus among the plural communications apparatuses suspending the transmission by the second communications apparatus when contents of data obtained from a first sensor of a first communications apparatus among the plural communications apparatuses and contents of data obtained from the second sensor of a second communications apparatus among the plural communications apparatuses are equivalent.

Abstract: A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.

Abstract: A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal.

Abstract: A multicore system includes multiple processor cores; a scheduler in each of the processor cores and allocating a process to the processor cores when having a master authority that is an authority to assign processes; and a master controller performing control to repeat until a process to be executed no longer exists, a cycle in which the schedulers transfer the master authority to another processor core after receiving the master authority and before assigning a process to the processor cores, discards the master authority after assigning the process to the processor cores, and enters a state of waiting to receive the master authority.

Abstract: A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.

Abstract: A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task.

Abstract: An assignment method executed by a given core of a multi-core processor includes identifying for each core, the number of storage areas to be used by a given thread and the number of storage areas used by threads already assigned; detecting for each core, a highest value from the number of storage areas used by the threads already assigned; determining whether a sum of a greater value of the detected highest value of a core selected as a candidate assignment destination and the number of storage areas to be used by the given thread, and the detected highest value of the cores excluding the selected core, is at most the number of storage areas of the shared resource; and assigning the given thread to the selected core, when the sum is at most the number of storage areas of the shared resource.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.

Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.