Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.