Patents by Inventor Hiromi Fukumura
Hiromi Fukumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118838Abstract: A method includes calculating a plurality of first index values indicating access loads from one or more first virtual storage devices accessing a first physical storage device of a plurality of physical storage devices, to the first physical storage device, in a case where access loads from the one or more first virtual storage devices to a plurality of second physical storage devices including the first physical storage device are equalized across the second physical storage devices, the plurality of second physical storage devices being associated with the one or more first virtual storage devices; and outputting a plurality of second index values indicating access loads from a plurality of virtual machines to the first physical storage device, the second index values being obtained by summing the calculated first index values for each virtual machine associated with each of the one or more first virtual storage devices.Type: ApplicationFiled: July 3, 2023Publication date: April 11, 2024Applicant: Fujitsu LimitedInventors: Kazutaka OGIHARA, Takashi SHIRAISHI, Masato OTSUKA, Naoya NISHIO, Hiromi FUKUMURA, Reiko KONDO
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Patent number: 9015517Abstract: In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.Type: GrantFiled: March 8, 2012Date of Patent: April 21, 2015Assignee: Fujitsu LimitedInventors: Kenji Okano, Kenji Gotsubo, Tadashi Yamada, Hiromi Fukumura
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Patent number: 8806276Abstract: A data processing system for performing stuck-at control includes system boards that process data, a crossbar unit having control units to control communication between each system board, and a system controller without causing an availability ratio of a computer system to fall. When a control unit fails, the crossbar unit sends, among IDs uniquely attached to each system board, the ID of each system board under the control of the failed control unit to the system controller. The system controller determines to which of partitions that logically divide a system each system board corresponding to the ID received from the crossbar unit belongs and sends a stop command to stop driving of each system board belonging to the determined partition.Type: GrantFiled: December 2, 2010Date of Patent: August 12, 2014Assignee: Fujitsu LimitedInventor: Hiromi Fukumura
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Patent number: 8769142Abstract: A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.Type: GrantFiled: June 28, 2010Date of Patent: July 1, 2014Assignee: Fujitsu LimitedInventors: Yuuji Konno, Hiroyuki Wada, Hiromi Fukumura, Hiroshi Murakami
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Publication number: 20140068166Abstract: A disclosed information processing apparatus includes: one or plural memories, each of which includes a self-refresh function; and a memory control unit that stops a patrol that includes reading and error correction with respect to a memory among the one or plural memories, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories. A disclosed memory control unit includes: a patrol unit that performs a patrol including reading and error correction with respect to a memory among one or plural memories that has a self-refresh function; and a controller that stops the patrol, upon starting self-refresh of the one or plural memories, and that restarts the patrol, upon stopping the self-refresh of the one or plural memories.Type: ApplicationFiled: August 20, 2013Publication date: March 6, 2014Applicant: FUJITSU LIMITEDInventors: Hiromi FUKUMURA, Katsuya SUGA
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Publication number: 20140068299Abstract: When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.Type: ApplicationFiled: August 27, 2013Publication date: March 6, 2014Applicant: FUJITSU LIMITEDInventors: HIDEYUKI KOINUMA, HIROMI FUKUMURA, MICHIHARU HARA, HIRONOBU KAGEYAMA, TOSHIO YOSHIDA
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Publication number: 20120233487Abstract: In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.Type: ApplicationFiled: March 8, 2012Publication date: September 13, 2012Applicant: FUJITSU LIMITEDInventors: Kenji OKANO, Kenji Gotsubo, Tadashi Yamada, Hiromi Fukumura
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Publication number: 20110173494Abstract: A data processing system for performing stuck-at control includes system boards that process data, a crossbar unit having control units to control communication between each system board, and a system controller without causing an availability ratio of a computer system to fall. When a control unit fails, the crossbar unit sends, among IDs uniquely attached to each system board, the ID of each system board under the control of the failed control unit to the system controller. The system controller determines to which of partitions that logically divide a system each system board corresponding to the ID received from the crossbar unit belongs and sends a stop command to stop driving of each system board belonging to the determined partition.Type: ApplicationFiled: December 2, 2010Publication date: July 14, 2011Applicant: Fujitsu LimitedInventor: Hiromi Fukumura
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Publication number: 20110004740Abstract: A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.Type: ApplicationFiled: June 28, 2010Publication date: January 6, 2011Applicant: FUJITSU LIMITEDInventors: Yuuji KONNO, Hiroyuki Wada, Hiromi Fukumura, Hiroshi Murakami
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Patent number: 7752378Abstract: A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one combination of the system board modules, and an inter-crossbar-unit conflict partition detecting unit for detecting a combination of partitions, which make a conflict between two of a plurality of crossbar units, for at least one combination of the two crossbar units on the basis of the determination result of the partition ID identifying unit, and the detection result of the partition ID match detecting unit.Type: GrantFiled: August 28, 2008Date of Patent: July 6, 2010Assignee: Fujitsu LimitedInventors: Hiromi Fukumura, Satoshi Nakagawa
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Publication number: 20080320272Abstract: A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one combination of the system board modules, and an inter-crossbar-unit conflict partition detecting unit for detecting a combination of partitions, which make a conflict between two of a plurality of crossbar units, for at least one combination of the two crossbar units on the basis of the determination result of the partition ID identifying unit, and the detection result of the partition ID match detecting unit.Type: ApplicationFiled: August 28, 2008Publication date: December 25, 2008Applicant: FUJITSU LIMITEDInventors: Hiromi FUKUMURA, Satoshi NAKAGAWA