Patents by Inventor Hiromi Kawashima
Hiromi Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030198083Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: ApplicationFiled: November 26, 2002Publication date: October 23, 2003Applicant: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 6611464Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: GrantFiled: October 7, 2002Date of Patent: August 26, 2003Assignee: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 6563738Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: GrantFiled: May 20, 2002Date of Patent: May 13, 2003Assignee: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita
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Publication number: 20030039139Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: ApplicationFiled: October 7, 2002Publication date: February 27, 2003Applicant: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Publication number: 20020136057Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: ApplicationFiled: May 20, 2002Publication date: September 26, 2002Applicant: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 6288945Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: GrantFiled: December 10, 1999Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Hiromi Kawashima, Shouichi Kawamura
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Publication number: 20010015932Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: ApplicationFiled: April 12, 2001Publication date: August 23, 2001Applicant: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 5815440Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.Type: GrantFiled: March 24, 1997Date of Patent: September 29, 1998Assignee: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 5770963Abstract: A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.Type: GrantFiled: May 8, 1995Date of Patent: June 23, 1998Assignee: Fujitsu LimitedInventors: Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
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Patent number: 5666314Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.Type: GrantFiled: June 6, 1995Date of Patent: September 9, 1997Assignee: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita
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Patent number: 5631597Abstract: A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.Type: GrantFiled: May 19, 1995Date of Patent: May 20, 1997Assignee: Fujitsu LimitedInventors: Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
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Patent number: 5608670Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.Type: GrantFiled: May 8, 1995Date of Patent: March 4, 1997Assignee: Fujitsu LimitedInventors: Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
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Patent number: 5592419Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.Type: GrantFiled: May 15, 1995Date of Patent: January 7, 1997Assignee: Fujitsu LimitedInventors: Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
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Patent number: 5576637Abstract: An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input.Type: GrantFiled: May 15, 1995Date of Patent: November 19, 1996Assignee: Fujitsu LimitedInventors: Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
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Patent number: 5452251Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.Type: GrantFiled: June 22, 1993Date of Patent: September 19, 1995Assignee: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita
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Patent number: 5428580Abstract: The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power.Type: GrantFiled: January 3, 1994Date of Patent: June 27, 1995Assignee: Fujitsu LimitedInventors: Hiromi Kawashima, Takao Akaogi
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Patent number: 5249156Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell parts which are arranged in an array, where each of the memory cell parts are made up of an electrically erasable programmable non-volatile memory cell and a volatile random access memory cell, a mode selection circuit for transferring data stored in the volatile random access memory cell into the electrically erasable programmable non-volatile memory cell for each of the memory cell parts in response to a store signal which specifies a store mode in which the data are stored in the electrically erasable programmable non-volatile memory cell of each of the memory cell parts, and a memory part for storing at least predetermined bits of the external memory address in response to the store signal.Type: GrantFiled: July 19, 1991Date of Patent: September 28, 1993Assignee: Fujitsu LimitedInventors: Ryoji Hagiwara, Hiromi Kawashima
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Patent number: 5173876Abstract: Where an electrically erasable and programmable non-volatile semiconductor memory element (EEPROM cell) for storing a setting and releasing of the software data protection has already been set in the logic state designating the software data protection setting state, and operation of setting the logical state designating the software data protection setting is not applied to the EEPROM cell even if the address and data for setting the software data protection is input. Further, where the logic state designating the releasing of the software data protection has been set in the electrically erasable and programmable non-volatile semiconductor memory element, the operation of setting the logical state designating the release of the software data protection is not set to the EEPROM cell, even if the address and the data for releasing the software data protection is input.Type: GrantFiled: September 19, 1990Date of Patent: December 22, 1992Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Hiromi Kawashima, Yoshinori Tsujimura
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Patent number: 5111136Abstract: A test mode input detection circuit for a semiconductor device comprises a first circuit including a group of transistors and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a transistor whose gate receives an output from the output terminal of the first circuit, and a transistor whose gate receives a power source voltage, these transistors being connected in series between the power source and a ground, a node between the transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.Type: GrantFiled: August 14, 1991Date of Patent: May 5, 1992Assignee: Fujitsu LimitedInventor: Hiromi Kawashima
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Patent number: 4937830Abstract: A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits.The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.Type: GrantFiled: May 18, 1988Date of Patent: June 26, 1990Assignee: Fujitsu LimitedInventors: Hiromi Kawashima, Ryoji Hagiwara