Abstract: In a RAID system, the power supplied to hard disks (HDDs) can be increased, and a plurality of types of HDDs can be installed. A plurality of HDD packs 33 are supplied with a single high voltage from a motherboard 28. The HDD packs 33 each accommodate, in a canister, an HDD 107, 181, 185 or 187 with different power supply specifications or communication interface specifications, as well as a DC/DC converter 109 to convert the power supply. Part of the HDD packs 33 have a data transfer interface conversion circuit 195 as well.

Abstract: A storage system capable of reducing the start-up time of disk drives is provided. If a power source monitor circuit itself is normal (S93), the power source monitor circuit reads a detection signal from a detection circuit, and checks power sources (S94). If the power sources are normal (S95), all disks are spun up (S96). When the spin-up of all disks is completed (S98), processing is completed. If either of two power sources fails (S95), the power source monitor circuit reports the fact to a host control logical part (S99). The power source monitor circuit clears its internal counter to zero (S100) and issues a drive command to HDDs (S101). When the spin-up of all disks is completed (S103), processing is completed. If there is a disk which has not yet been spun up, the power source monitor circuit sets the internal counter to n+1 (S104) and returns to Step S101.

Abstract: A disk array system including: at least one channel control portion for receiving an input/output request of data from an information processor and exchanging the data with the information processor; at least one disk control portion for exchanging the data with a disk drive in accordance with the input/output request; a cache memory for storing the data exchanged between the channel control portion and the disk control portion; a cache switch for forming a communication path between the channel control portion and the cache memory; a shared memory for storing the input/output request exchanged between the channel control portion and the disk control portion; and at least one disk drive unit including the disk drive, and a canister for storing the disk drive; wherein the canister is provided with a power unit for supplying electric power to the drive device for driving the disk drive.

Abstract: A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the channel control portion, the disk control portion, the cache memory, the cache switch, the shared memory and the power unit, wherein: each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory includes a control board having a plurality of electronic circuits different in operating voltage, and a voltage converter for converting a single input voltage into voltages for operating the electronic circuits respectively; and the power unit supplies a voltage to the voltage converter provided in each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory.

Abstract: The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths.

Abstract: A disk array device and a method of supplying power to a disk array device to which power is supplied by at least two AC inputs are provided. Where at least two AC/DC power-supply groups are provided in correspondence with each of the AC inputs and each AC/DC power-supply group includes at least two AC/DC power supplies that are connected to the AC input corresponding to that group, outputs from the AC/DC power supplies are summed separately for each group to obtain group total outputs for each group, and the group total outputs are input to each of a plurality of loads in the disk array device to provide power to each of the loads.

Abstract: A disk array device having two or more disk units, each disk unit including at least one disk drive, at least either of said disk units having parity bits carrying data recovery information, comprises at least one backup battery provided for each of said disk unit.

Abstract: A power source control apparatus for a disk subsystem includes a plurality of hard disk drives (HDDs) each with two systems of fiber channel interface ports, an HDD drive section, and an HDD control logic section. The HDD drive section includes two systems of fiber channel control sections, each of which includes a fiber channel interface and a fiber channel control interface. The HDD control logic section includes two systems of HDD control logics that control read/write accesses to the HDDs. Fiber channel control signals are supplied from the HDD control logics to the fiber channel control interfaces, respectively, and the fiber channel control signals are also used to control the power source of the HDD drive section.

Abstract: A plurality of electronic devices such as magnetic disk devices may be connected to a fiber channel arbitrated loop. Each of the electronic device includes a port bypass circuit that selectively separates the electronic device from the fiber channel arbitrated loop, a margin test circuit added to an input/output circuit of the electronic device connected to the port bypass circuit, and a signal line that provides a control signal to the margin text circuit from outside of the electronic device. The electronic device is selectively connected to and operated on the fiber channel arbitrated loop while the margin test circuit is made functional by the control signal to generate an error.

Abstract: Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11.

Abstract: A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same.

Abstract: Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11.

Abstract: A data reproducing circuit having a magnetic head for reading data from a recording medium, an adaptive equalization circuit for optimizing the waveform of a read signal, a discriminator circuit for discriminating an output signal of the adaptive equalization circuit and outputting a discriminated signal to an upper stage circuit, a format detecting circuit for detecting a pattern of signals written on the recording medium from outputs of the magnetic head, an expected value generating circuit for generating an expected value of the waveform of the read signal in accordance with an output of the adaptive equalization circuit and an output of the discriminator circuit, and an error detecting circuit for generating an error signal representing a difference between an output of the adaptive equalization circuit and an output of the expected value generating circuit.

Abstract: A signal detection circuit of a magnetic recording and reproducing apparatus generates a clock signal synchronized with peaks of a reproduced signal read from a magnetic recording medium on which data have been recorded by a (d, k) run-length code, and determines "1" or "0" with respect to a discrimination threshold based on an absolute value of a peak of the reproduced waveform at a timing synchronized with the clock signal. The signal detection circuit comprises a quantizer for quantizing the reproduced signal in synchronism with the clock signal to produce a quantized signal, a multi-stage shift register for delaying the clock signal in synchronism with the clock signal, and threshold generation means for comparing the quantized signal supplied from the final stage of the multi-stage shift register and the quantized signal representing the current threshold to dynamically generate a new relevant threshold in accordance with the difference in the comparison.

Abstract: A magnetic head for recording and reproducing information on and from a flexible magnetic recording tape. The active face of tape supporting protrusions formed in the magnetic head is so configured that the contacting area between the supporting protrusion and the recording tape is smaller at both end portions of the protrusion than an intermediate portion thereof as viewed in the direction widthwise of the recording tape, whereby improved contacting state and floating state between the magnetic head and the recording tape can be assured over the whole width of the flexible recording tape.