Patents by Inventor Hiromi Nanba
Hiromi Nanba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080296291Abstract: A warm wave generating system includes a direct-current power supply, a frequency generator to output a variable signal wave at a predetermined frequency range, a transformer in which a primary coil through which a direct current outputted from the direct-current power supply can pass is opposed to a secondary coil through which the signal wave outputted from the frequency generator can pass, and a heating element connected to the direct-current power supply via the primary coil of the transformer. The direct current, which is modulated by the signal wave passing through the primary coil of the transformer and then through the secondary coil, is used to allow the heating element to generate heat.Type: ApplicationFiled: June 5, 2006Publication date: December 4, 2008Inventors: Hiromi Nanba, Masaaki Harita
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Patent number: 6936473Abstract: The present invention is directed to a method of preparing a biological sample for quantification which includes an element to be quantified. A volume of biological sample is collected without quantifying the volume thereof to mix with a specified volume of an aqueous solution. Absorptivity of an indicating material in the aqueous solution is measured. Absorptivity of the indicating material in the collected biological sample mixed with the specified volume of the aqueous solution is measured. Next, a dilution ratio of the biological sample is calculated using the absorptivity of the indicating material in the specified volume of the aqueous solution and the absorptivity of the indicating material in the biological sample mixed with the specified volume of the aqueous solution.Type: GrantFiled: November 29, 2001Date of Patent: August 30, 2005Assignee: Leisure, Inc.Inventors: Hiromi Nanba, Osamu Koga, Masatoshi Horita, Yoshio Ohta
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Patent number: 6922163Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.Type: GrantFiled: February 4, 2004Date of Patent: July 26, 2005Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Toru Mizutani
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Publication number: 20040227546Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.Type: ApplicationFiled: February 4, 2004Publication date: November 18, 2004Applicant: FUJITSU LIMITEDInventors: Hiromi Nanba, Toru Mizutani
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Patent number: 6819273Abstract: An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.Type: GrantFiled: February 19, 2003Date of Patent: November 16, 2004Assignee: Fujitsu LimitedInventors: Tohru Mizutani, Hiromi Nanba, Atsushi Matsuda, Atsushi Hitaka, Masashi Okubo, Yoshinori Yoshikawa, Kenichi Minobe
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Publication number: 20040141888Abstract: An object of the present invention is to reduce the cost in blood test and to simplify the operation thereof.Type: ApplicationFiled: January 7, 2004Publication date: July 22, 2004Applicant: LEISURE, INC.Inventors: Hiromi Nanba, Osamu Koga, Masatoshi Horita, Yoshio Ohta
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Patent number: 6738001Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.Type: GrantFiled: February 1, 2002Date of Patent: May 18, 2004Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Toru Mizutani
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Patent number: 6717457Abstract: A semiconductor device with temperature compensation functions and a temperature change detecting device which detect temperature changes accurately, without requiring extra mounting space. A sensor unit is composed of first semiconductor components (first-type resistors) having a certain temperature coefficient and second semiconductor components (second-type resistors) having a different temperature coefficient. They are located in the vicinity of a processing circuit that needs temperature compensation. Changes in the temperature of the processing circuit are detected by a temperature change detector which observes a certain property (e.g., resistance) of the first and second semiconductor components constituting the sensor unit. A temperature corrector corrects functions of the processing circuit according to the detection result provided from the temperature change detector.Type: GrantFiled: March 18, 2002Date of Patent: April 6, 2004Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Kenichi Minobe
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Publication number: 20030179118Abstract: An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.Type: ApplicationFiled: February 19, 2003Publication date: September 25, 2003Inventors: Tohru Mizutani, Hiromi Nanba, Atsushi Matsuda, Atsushi Hitaka, Masashi Okubo, Yoshinori Yoshikawa, Kenichi Minobe
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Publication number: 20030067344Abstract: A semiconductor device with temperature compensation functions and a temperature change detecting device which detect temperature changes accurately, without requiring extra mounting space. A sensor unit is composed of first semiconductor components (first-type resistors) having a certain temperature coefficient and second semiconductor components (second-type resistors) having a different temperature coefficient. They are located in the vicinity of a processing circuit that needs temperature compensation. Changes in the temperature of the processing circuit are detected by a temperature change detector which observes a certain property (e.g., resistance) of the first and second semiconductor components constituting the sensor unit. A temperature corrector corrects functions of the processing circuit according to the detection result provided from the temperature change detector.Type: ApplicationFiled: March 18, 2002Publication date: April 10, 2003Applicant: FUJITSU LIMITEDInventors: Hiromi Nanba, Kenichi Minobe
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Patent number: 6535039Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.Type: GrantFiled: August 6, 2001Date of Patent: March 18, 2003Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Tohru Mizutani, Makoto Ikeshita, Masato Takeyabu
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Publication number: 20020153316Abstract: An object of the present invention is to reduce the cost in blood test and to simplify the operation thereof.Type: ApplicationFiled: November 29, 2001Publication date: October 24, 2002Inventors: Hiromi Nanba, Osamu Koga, Masatoshi Horita, Yoshio Ohta
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Publication number: 20020105454Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.Type: ApplicationFiled: February 1, 2002Publication date: August 8, 2002Applicant: FUJITSU LIMITEDInventors: Hiromi Nanba, Toru Mizutani
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Publication number: 20020063590Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.Type: ApplicationFiled: August 6, 2001Publication date: May 30, 2002Applicant: FUJITSU LIMITEDInventors: Hiromi Nanba, Tohru Mizutani, Makoto Ikeshita, Masato Takeyabu
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Publication number: 20010015338Abstract: An object of the present invention is to reduce the cost in blood test and to simplify the operation thereof.Type: ApplicationFiled: January 4, 2001Publication date: August 23, 2001Inventors: Hiromi Nanba, Osamu Koga, Yoshio Ohta
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Patent number: 5038393Abstract: In a character reading apparatus, a slip image having three reference marks printed at three of the four predetermined corners of the slip is stored in an image buffer. The image in the image buffer is scanned to detect the three reference marks. A feed orientation of the slip is determined on the basis of the layout of the three reference marks. Data can be read on the basis of the detected three reference marks and the determined feed orientation of the slip.Type: GrantFiled: December 17, 1990Date of Patent: August 6, 1991Assignee: Kabushiki Kaisha ToshibaInventor: Hiromi Nanba
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Patent number: 4872062Abstract: A facsimile apparatus comprises first and second lamps and a controller. The controller selectively sends a first control signal to the first lamp and a second control signal to the second lamp in accordance with whether or not a data sheet contains a pattern described in a drop-out color. The first lamp emits first light having a first wavelength characteristic in accordance with the incoming first control signal. The second lamp emits second light having a second wavelength characteristic different from the first wavelength characteristic in accordance with the incoming second control signal.Type: GrantFiled: August 16, 1988Date of Patent: October 3, 1989Assignee: Kabushiki Kaisha ToshibaInventor: Hiromi Nanba
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Patent number: RE40168Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.Type: GrantFiled: December 22, 2003Date of Patent: March 25, 2008Assignee: Fujitsu LimitedInventors: Hiromi Nanba, Tohru Mizutani, Makoto Ikeshita, Masato Takeyabu