Patents by Inventor Hiromi Niiyama

Hiromi Niiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for fabricating a metal wiring and metal contact in a semicondutor device
    Patent number: 6794286
    Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisako Aoyama, Kyoichi Suguro, Hiromi Niiyama, Hitoshi Tamura, Hisataka Hayashi, Tomonori Aoyama, Gaku Minamihaba, Tadashi Iijima
  • Method of manufacturing a semiconductor device using a polymer film pattern
    Patent number: 6465290
    Abstract: Claimed and disclosed is a method of manufacturing a semiconductor device, the method comprising the steps of forming a dummy gate on a semiconductor substrate, forming a source-drain diffusion region by introducing an impurity into the semiconductor substrate having the dummy gate as a mask, removing the dummy gate to form an opening, and forming a gate electrode within the opening with a gate insulating film formed below the gate electrode. The dummy gate is further formed by coating the semiconductor substrate with a polymer having a higher carbon content than hydrogen content so as to form a polymer film, forming a photoresist pattern on the polymer film, and transferring the pattern shape of the photoresist pattern onto the polymer film.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kouji Matsuo, Atsushi Murakoshi, Yasuhiko Sato, Hiromi Niiyama
  • Pattern-forming method and lithographic system
    Patent number: 6093931
    Abstract: A rough pattern exceeding the resolution limit of light exposure is formed by light resolution. A fine pattern not exceeding the resolution limit of light exposure is formed by charge-beam exposure. Combining the rough pattern and the fine pattern produces a desired pattern. The sharing of the work between light exposure and charge-beam exposure exhibits the high throughput of light exposure and the excellent resolving power of charge-beam exposure.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Sugihara, Hiromi Niiyama, Shunko Magoshi, Atsushi Ando, Tetsuro Nakasugi, Shinji Sato, Yumi Watanabe, Yosimitu Kato, Toru Shibata, Katsuya Okumura
  • Method of making a semiconductor device
    Patent number: 6090699
    Abstract: A method of making a semiconductor device includes a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisako Aoyama, Kyoichi Suguro, Hiromi Niiyama, Hitoshi Tamura, Hisataka Hayashi, Tomonori Aoyama, Gaku Minamihaba, Tadashi Iijima
  • Pattern forming method through combined electron beam and light exposure utilizing multiple heat steps
    Patent number: 6020107
    Abstract: A rough pattern is formed on a chemically amplified resist by light exposing, and a fine pattern is formed by EB exposing. The resist is heated not only after EB exposing but also after light exposing. After this, the resist on which the rough and the fine patterns are formed is developed. As a result of this, diffusion or deactivation of an acid can be suppressed, and dimensional errors can be reduced.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: February 1, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromi Niiyama, Shinji Sato, Shunko Magoshi
  • Pattern-forming method and lithographic system
    Patent number: 5994030
    Abstract: A rough pattern exceeding the resolution limit of light exposure is formed by light resolution. A fine pattern not exceeding the resolution limit of light exposure is formed by charge-beam exposure. Combining the rough pattern and the fine pattern produces a desired pattern. The sharing of the work between light exposure and charge-beam exposure exhibits the high throughput of light exposure and the excellent resolving power of charge-beam exposure.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Sugihara, Hiromi Niiyama, Shunko Magoshi, Atsushi Ando, Tetsuro Nakasugi, Shinji Sato, Yumi Watanabe, Yosimitu Kato, Toru Shibata, Katsuya Okumura
  • Semiconductor device having a wiring layer with a barrier layer
    Patent number: 5592024
    Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: January 7, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisako Aoyama, Kyoichi Suguro, Hiromi Niiyama, Hitoshi Tamura, Hisataka Hayashi, Tomonori Aoyama, Gaku Minamihaba, Tadashi Iijima