Patents by Inventor Hiromi Nishino
Hiromi Nishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8830439Abstract: Provided is a display panel using polymer network liquid crystal in which a monomer unreacted region is reduced and a thin-film transistor can be prevented from being irradiated with light energy. In the display panel, a black matrix (22a) is provided as an element having a light-shielding property in a first substrate (2a), a pixel electrode (37) and a thin-film transistor (32) serving as a switching element for driving the pixel electrode (37) are provided in a second substrate (3a), polymer network liquid crystal (11) is filled between the first substrate (2a) and the second substrate (3a), a cover portion (221) that is part of the black matrix (22a) provided in the first substrate (2a) faces the thin-film transistor (32) provided in the second substrate (3a), and the outer periphery of the cover portion (221) is located outside the outer periphery of a channel region by a specified dimension or more.Type: GrantFiled: April 21, 2011Date of Patent: September 9, 2014Assignee: Sharp Kabushiki KaishaInventors: Isao Asako, Yukinori Nakagawa, Hiromi Nishino, Shinji Shimada
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Publication number: 20130077009Abstract: Provided is a display panel using polymer network liquid crystal in which a monomer unreacted region is reduced and a thin-film transistor can be prevented from being irradiated with light energy. In the display panel, a black matrix (22a) is provided as an element having a light-shielding property in a first substrate (2a), a pixel electrode (37) and a thin-film transistor (32) serving as a switching element for driving the pixel electrode (37) are provided in a second substrate (3a), polymer network liquid crystal (11) is filled between the first substrate (2a) and the second substrate (3a), a cover portion (221) that is part of the black matrix (22a) provided in the first substrate (2a) faces the thin-film transistor (32) provided in the second substrate (3a), and the outer periphery of the cover portion (221) is located outside the outer periphery of a channel region by a specified dimension or more.Type: ApplicationFiled: April 21, 2011Publication date: March 28, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Isao Asako, Yukinori Nakagawa, Hiromi Nishino, Shinji Shimada
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Publication number: 20120154733Abstract: Provided is a liquid crystal display panel that employs polymer network liquid crystals and that can prevent a separation between a substrate and a liquid crystal layer. The liquid crystal display panel includes a color filter 1 and a TFT array substrate 2 that face each other in a substantially parallel manner with a prescribed gap therebetween, a layer of polymer network liquid crystals 33 formed between the color filter 1 and the TFT array substrate 2, and a layer of a sealing material 34 that encloses and seals the polymer network liquid crystals 33. In a region enclosed by the sealing material 34 in the color filter 1, first spacers 12a that define the gap between the color filter 1 and the TFT array substrate 2 are formed. A total cross-sectional area of the first spacers 12a and an area of the region enclosed by the sealing material 34 satisfy the following condition: (the total cross-sectional area of the first spacers 12a)/(the area of the region enclosed by the sealing material 34)=0.001 to 0.017.Type: ApplicationFiled: May 21, 2010Publication date: June 21, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yukinori Nakagawa, Isao Asako, Hiromi Nishino, Shinji Shimada
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Patent number: 6917408Abstract: A thin tantalum film deposited on an insulating substrate is patterned to form an electrode wiring of a first layer which is the lowermost layer for constituting the input lead wiring and, then, an SiNx film is formed as the gate-insulating film. An electrode wiring of a second layer formed of an ITO (indium tin oxide) film and an electrode wiring of a third layer formed of a thin tantalum film are laminated on the gate-insulating film in a manner that the plurality of electrode wiring portions possess widths W1, W2 and W3 which are 300 ?m or less at the greatest. Here, the electrode wiring of the second layer and the electrode wiring of the third layer are so arranged as will not be overlapped on the edge portions on both sides of the electrode wiring of the first layer.Type: GrantFiled: December 2, 2002Date of Patent: July 12, 2005Assignee: Sharp Kabushiki KaishaInventor: Hiromi Nishino
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Publication number: 20030103184Abstract: A thin tantalum film deposited on an insulating substrate is patterned to form an electrode wiring of a first layer which is the lowermost layer for constituting the input lead wiring and, then, an SiNx film is formed as the gate-insulating film. An electrode wiring of a second layer formed of an ITO (indium tin oxide) film and an electrode wiring of a third layer formed of a thin tantalum film are laminated on the gate-insulating film in a manner that the plurality of electrode wiring portions possess widths W1, W2 and W3 which are 300 &mgr;m or less at the greatest. Here, the electrode wiring of the second layer and the electrode wiring of the third layer are so arranged as will not be overlapped on the edge portions on both sides of the electrode wiring of the first layer.Type: ApplicationFiled: December 2, 2002Publication date: June 5, 2003Inventor: Hiromi Nishino
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Patent number: 5586385Abstract: A method of manufacturing a thin film magnetic head includes the steps of, integrally forming a resin mold of a prescribed thickness by insert molding on a substrate including an element portion and a wiring connection portion, and shaping in the vicinity of the element portion an end of the substrate to form a magnetic recording medium sliding surface. According to this method, the manufacturing process can be simplified, and the lower manufacturing cost and higher yield can be implemented.Type: GrantFiled: February 13, 1996Date of Patent: December 24, 1996Assignee: Sharp Kabushiki KaishaInventors: Hiromi Nishino, Akiyoshi Fujii
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Patent number: 5252988Abstract: A thermal head for a thermal recording machine including an insulating substrate which is composed of a printed circuit board made of a heat resistant resin and covered with a copper film, a plurality of thermal resistors disposed on the insulating substrate in the direction corresponding to the scanning, discrete electrodes electrically connecting first ends of the thermal resistors to a control element, a common electrode electrically connecting the other ends of the thermal resistors together, a heat releasing layer formed of the copper film of the insulating substrate on the lower portions of the thermal resistors, and a thermal accumulating layer of a polyimide resin covering the heat releasing layer.Type: GrantFiled: December 11, 1990Date of Patent: October 12, 1993Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Katayama, Hiroshi Suzuki, Masato Kawanishi, Mitsuhiko Yoshikawa, Toshitaka Tamura, Takatoshi Mizoguchi, Hiromi Nishino, Akiyoshi Fujii, Takayuki Taminaga, Katsuyasu Deguchi
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Patent number: 5183725Abstract: An electrode pattern forming method comprising the steps of: forming a transparent conductive film on a substrate, covering said transparent conductive film with an aluminum film, forming a resist material film for etching on said aluminum film, exposing said resist material film followed by developing by immersing said substrate in an electrolyte to form a resist pattern, and patterning said aluminum film using said resist pattern as a mask;the formation of said resist pattern in said electrolyte being conducted with another transparent conductive film which is in direct contact with said electrolyte and electrically connected to said aluminum film.Type: GrantFiled: October 1, 1990Date of Patent: February 2, 1993Assignee: Sharp Kabushiki KaishaInventors: Hiromi Nishino, Keiji Tarui, Hideyuki Toyoshi, Tatsuo Morita