Abstract: According to one embodiment, a semiconductor memory device includes a mounting board and memory dies. The memory dies include first pad electrodes, first pull-up circuits connected to the first pad electrodes, a first output circuit that outputs a first parameter to the first pull-up circuits, first pull-down circuits connected to the first pad electrodes, a second output circuit that outputs a second parameter to the first pull-down circuits, a second pad electrode, a second pull-up circuit connected to the second pad electrode, a third output circuit that is connected to the second pad electrode, a third pad electrode, a second pull-down circuit connected to the third pad electrode, and a fourth output circuit that is connected to the third pad electrode. The second pad electrode of the second memory die is connected to the third pad electrode of the first memory die.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes a mounting board and memory dies. The memory dies include first pad electrodes, first pull-up circuits connected to the first pad electrodes, a first output circuit that outputs a first parameter to the first pull-up circuits, first pull-down circuits connected to the first pad electrodes, a second output circuit that outputs a second parameter to the first pull-down circuits, a second pad electrode, a second pull-up circuit connected to the second pad electrode, a third output circuit that is connected to the second pad electrode, a third pad electrode, a second pull-down circuit connected to the third pad electrode, and a fourth output circuit that is connected to the third pad electrode. The second pad electrode of the second memory die is connected to the third pad electrode of the first memory die.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory configured to store data; an error correcting circuit configured to correct an error in data read from the memory, and to generate a first signal of a first state, which is transmitted to an external along with the data if the error in the data cannot be corrected; and a first pin configured to transmit the first signal to the external and receive a data mask signal from the external.

Abstract: According to one embodiment, a semiconductor memory device includes, a memory cell array, a first clock signal line, a second clock signal line to which first and second input/output buffer circuits are coupled in the order from one end toward the other end, a first buffer coupled to the one end of the second clock signal line, and a second buffer coupled to the other end of the second clock signal line. When a write operation is performed, a clock signal is input to the first and second input/output buffer circuits through the first buffer, and when a read operation is performed, a clock signal is input to the first and second input/output buffer circuits through the second buffer.

Abstract: According to one embodiment, a semiconductor memory device includes, a memory cell array, a first clock signal line, a second clock signal line to which first and second input/output buffer circuits are coupled in the order from one end toward the other end, a first buffer coupled to the one end of the second clock signal line, and a second buffer coupled to the other end of the second clock signal line. When a write operation is performed, a clock signal is input to the first and second input/output buffer circuits through the first buffer, and when a read operation is performed, a clock signal is input to the first and second input/output buffer circuits through the second buffer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory configured to store data; an error correcting circuit configured to correct an error in data read from the memory, and to generate a first signal of a first state, which is transmitted to an external along with the data if the error in the data cannot be corrected; and a first pin configured to transmit the first signal to the external and receive a data mask signal from the external.

Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.

Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.

Abstract: A semiconductor memory device includes a first pad which outputs data to the outside; an output driver coupled to the first pad; a calibration circuit which adjusts impedance of the output driver; and a controller. The controller controls a calibration operation by the calibration circuit, in response to a first command received from the outside, and performs a write operation on a mode resister, in response to a second command received from the outside, the second command being different from the first command.

Abstract: According to one embodiment, a semiconductor device includes a first pad in a first region between a memory region of a semiconductor chip and a first end portion of the semiconductor chip; a second pad in a second region between the memory region and a second end portion of the semiconductor chip, the second end portion being opposite to the first end portion; an output circuit coupled to the second pad; and a calibration circuit which is coupled to the first pad and regulates an impedance of the output circuit, the calibration circuit including a first circuit in the first region and a second circuit in the second region.

Abstract: According to one embodiment, a semiconductor memory device includes first and second banks, each of the first and second banks comprising a memory cell array; a data buffer a data buffer which is shared by the first and second banks, and stores write data which is to be written to the first and second banks and read data which is read from the first and second banks; a correcting circuit which is shared by the first and second banks, and corrects an error of the read data; and a multiplexer which switches a connection between the first bank and the data buffer and correcting circuit, and switches a connection between the second bank and the data buffer and correcting circuit. The multiplexer is disposed between the data buffer and the correcting circuit.

Abstract: According to one embodiment, a sense amplifier detects data stored in a memory cell based on potentials of bit lines of a bit line pair where bit line pairs are provided to correspond to columns of a memory cell array, respectively. Dummy cells are provided to correspond to rows of the memory cell array, respectively to simulate a read operation of the memory cells. A dummy bit line pair is driven in a complementary manner based on data read from the dummy cell. A read control unit controls the read operation of the memory cells based on the potential difference between dummy bit lines of the dummy bit line pair.

Abstract: Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

Abstract: Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a tag latch simultaneously with a data value being clocked into a data latch. The tag value and initial CAM element values begin propagating through comparison logic. After a delay, the data value is written from the data latch to a CAM element. After the tag value and initial CAM values propagate through the comparison logic to produce comparison outputs, but before the newly written data value propagates through the comparison logic and changes the comparison outputs, the comparison outputs are latched. The comparison outputs can then be processed as if the data values in the CAM elements had not been changed by the write operation.

Abstract: This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.