Patents by Inventor Hiromi Ogasawara

Hiromi Ogasawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7256100
    Abstract: A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation material is deposited on the entire surface so that the trench is filled with the first material and the first material covers the first and second regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first region is exposed while the mask layer formed on the second region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material. Finally, the second material is subjected to the chemical mechanical polish so that mask layer formed on the first and second regions is substantially exposed.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: August 14, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiromi Ogasawara
  • Patent number: 6943109
    Abstract: A semiconductor element has an upper wiring layer and a lower wiring layer. The upper and lower wiring layers communicate with each other via a via-hole. The via-hole is filled with W. Before W is filled in the via-hole by a CVD process to connect the lower wiring layer to the upper wiring layer, a cleaning gas is supplied into the via-hole to remove particular substances, which would otherwise result in high resistance. Subsequent to the cleaning step, the W portion is formed in the via-hole. Since the high resistance substances are removed from the via-hole before the formation of the W portion, the semiconductor element (or the via-hole) has a low resistance and high reliability.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: September 13, 2005
    Assignee: Oki Electric Industrial Co., Ltd.
    Inventors: Hiromi Ogasawara, Masashi Takahashi
  • Publication number: 20040072417
    Abstract: A semiconductor element has an upper wiring layer and a lower wiring layer. These layers communicate with each other via a via-hole. The via-hole is filled with W. Before W is filled in the via-hole by a CVD process to connect the lower wiring layer to the upper wiring layer, a cleaning gas is supplied into the via-hole to remove particular substances, which would otherwise result in high resistance. Subsequent to the cleaning step, the W portion is formed in the via-hole. Since the high resistance substances are removed from the via-hole before the formation of the W portion, the semiconductor element (or the via-hole) has a low resistance and high reliability.
    Type: Application
    Filed: July 11, 2003
    Publication date: April 15, 2004
    Inventors: Hiromi Ogasawara, Masashi Takahashi
  • Publication number: 20030036246
    Abstract: A method of manufacturing a semiconductor device comprises providing a semiconductor substrate that includes a first active region having a first area, a second active region having a second area that is larger than the first area and an isolation region. Then, a mask layer is selectively formed on the first and second active regions. A trench is formed on the isolation region of the substrate. A first isolation material is deposited on the trench and the mask layer so that the trench is filled with the first material and the first material covers the first and second active regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first active region is exposed while the mask layer formed on the second active region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material.
    Type: Application
    Filed: March 14, 2002
    Publication date: February 20, 2003
    Inventor: Hiromi Ogasawara