Abstract: In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.

Abstract: In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.

Abstract: A jumper circuit is provided for enabling the switching of the mode in the case that a bare chip is detected as being defective, wherein data that has been inputted to/outputted from a bare chip detected as being defective is inputted to/outputted from a good function chip for repair mounted on the rear surface of a module substrate so that the good function chip functions in place of the bare chip that has been detected as being defective. Thereby, a semiconductor memory module is obtained that can be repaired in the case that a bare chip is detected as being defective from among a plurality of bare chips while effectively utilizing bare chips other than the bare chip that has become defective from among the plurality of bare chips.

Abstract: In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

Abstract: A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

Abstract: A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.

Abstract: A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.