Patents by Inventor Hiromi Sadaie

Hiromi Sadaie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5811862
    Abstract: A semiconductor device having a multi-value memory including an offset ROM and a manufacturing method thereof can be obtained which allows accurate formation of a source/drain region and an offset region. In this semiconductor device, an offset source/drain region is provided so that a side end portion thereof is positioned substantially in flush with a lower end of an external surface of a sidewall insulating film placed on a side surface of a first gate electrode. Consequently, the offset source/drain region can be formed easily in a self-aligned manner by ion implantation using the sidewall insulating film as a mask, thereby forming the offset region accurately in a self-aligned manner.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: September 22, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Semiconductor Software Corporation
    Inventors: Akira Okugaki, Shinichi Mori, Kenji Koda, Hiromi Sadaie