Patents by Inventor Hiromi Wakabayashi

Hiromi Wakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7303691
    Abstract: A polishing method includes a slurry adjusting step for adjusting a polishing slurry containing silica particles so that the number of silica particles having a composition ratio of Si/O of 50–60 wt %/40–50 wt %, a modulus of elasticity of 1.4×1010 Pa or higher and a particle size of 1 ?m or larger is 3000 pcs/ml or less. A semiconductor wafer is polished using the polishing slurry adjusted in the slurry adjusting step.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: December 4, 2007
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuaki Kozasa, Motoharu Yamada, Yasuhiro Tomita, Hiromi Wakabayashi
  • Publication number: 20070059935
    Abstract: A polishing method includes a slurry adjusting step for adjusting a polishing slurry containing silica particles so that the number of silica particles having a composition ratio of Si/O of 50-60 wt %/40-50 wt %, a modulus of elasticity of 1.4×1010 Pa or higher and a particle size of 1 ?m or larger is 3000 pcs/ml or less. A semiconductor wafer is polished using the polishing slurry adjusted in the slurry adjusting step.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 15, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Kazuaki Kozasa, Motoharu Yamada, Uasuhiro Tomita, Hiromi Wakabayashi
  • Patent number: 5866477
    Abstract: The present invention is intended to provide a polishing method for a chamfered portion of a semiconductor silicon substrate, wherein edge relief of an oxidized silicon layer and/or an extrinsic gettering layer, and mirror polishing of chamfered portion can be performed at the same time for the semiconductor silicon substrate having the oxidized silicon layer and/or extrinsic gettering layer on the bottom thereof. The semiconductor silicon substrate is tilted at a designated chamfered angle .theta. with respect to an axis of a buff being mounted in a polishing apparatus to mirror polish the chamfered portion on one side. Then, the semiconductor silicon substrate is reversed, and the mirror polish is performed for the chamfered portion on the other side. A mean diameter of the colloidal silica constituting the polish liquid is 50.about.150 nm, the pH value of the polish liquid is 10.about.11, a specific gravity at 20.degree. C. is 1.about.1.5, and a concentration is 30.about.50 wt %.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: February 2, 1999
    Assignee: Komatsu Electric Metals Co., Ltd.
    Inventors: Yoshihiro Ogawa, Hiromi Wakabayashi, Kunimi Yoshimura