Abstract: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

Abstract: Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

Abstract: Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

Abstract: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

Abstract: The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and secure data integrity. The bus bridge is defined with clear master-slave protocol. The bus bridge normally involves the use of two arbiters. The arbiter on the primary bus needs to operate differently from the arbiter on the secondary bus due to real system time constraints. This invention defines a bus arbiter that allows for a dominant bus master to receive an immediate grant of control on the bus. This immediate grant bus arbiter never relinquishes the bus if another lower priority master makes a bus request. This makes predictable real time data transfer possible.

Abstract: A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

Abstract: A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

Abstract: This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.

Abstract: The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus device if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus. Address and data FIFO buffers are used for writes to a second bus device.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

Abstract: A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

Abstract: This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.

Abstract: The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus.

Abstract: The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and secure data integrity. The bus bridge is defined with clear master-slave protocol. The bus bridge normally involves the use of two arbiters. The arbiter on the primary bus needs to operate differently from the arbiter on the secondary bus due to real system time constraints. This invention defines a bus arbiter that allows for a dominant bus master to receive an immediate grant of control on the bus. This immediate grant bus arbiter never relinquishes the bus if another lower priority master makes a bus request. This makes predictable real time data transfer possible.