Abstract: A propeller shaft (1) that is a power transmission shaft has a shaft member (2) as a tubular body made of iron-based metal and a balance weight (3) made of iron-based metal and welded to an outer peripheral surface of this shaft member (2). At least a part of the balance weight (3) of the propeller shaft (1) is covered with a sacrificial metal coating (4) made of sacrificial corrosion prevention material that contains metal whose ionization tendency is higher than that of metal forming the shaft member (2). With this, it is possible to suppress local progression of corrosion at a periphery of the balance weight (3) and improve durability of the propeller shaft (1).

Abstract: A data processing device includes a first power-on reset circuit, a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit, a low voltage detect circuit, a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state, a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit, and a power supply node providing a power to the data processing device.

Abstract: A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit.

Abstract: A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit.

Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.

Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.

Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.

Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.

Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Abstract: A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.

Abstract: The efficiency of block data transfer can be increased without little increasing physical circuit scales. Since a data transfer control device uses a random access memory accessible by a central processing unit as a buffer area for temporarily storing read data in dual address transfer, it does not need to have a dedicated FIFO buffer and the like in itself. Since a buffer area allocated to the random access memory or its size is programmable by the central processing unit, capacity necessary to the system may be allocated to the buffer to avoid conflict with a work area by the central processing unit.

Abstract: No matter how large or small a data capacity in an address space is, code efficiency and data processing performance are improved without deteriorating the usage comfort of a CPU. Since a data processor is configured employing an instruction control unit (CONT) capable of changing interpretation of identical instructions according to dynamic switching of operation modes, dynamic switching can be made between the operation mode that limits data areas in an address space to give higher priority to higher code efficiency and quicker instruction fetch, and the operation mode that eliminates limitations on usable data areas to the fullest extent possible. Thereby, the advantages of instructions of contracted form and the like can be offered without deteriorating the usage comfort of the CPU.

Abstract: A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.