Patents by Inventor Hiromichi Kuwano

Hiromichi Kuwano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070153413
    Abstract: A system and method of the companion chip monitoring the active head chip over the conventional 4 wire structure, including when the active head chip goes into a sleep state. Advantageously, the companion chip remains operational and detects changes of the voltage on the DX and DY line, even when the active head chip determines a fault and goes into a sleep state. Further, the companion chip can determine which fault was detected by the active head chip using a read back function, such as analyzing an internal register of the active head chip.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Hiromichi Kuwano, Motomu Hashizume, Naoko Jinguji
  • Patent number: 6819516
    Abstract: An unsafe detection circuit for detecting a kickback signal including an input circuit for inputting a kickback signal, a circuit for detecting the presence or absence of said kickback signal, and a fault detection circuit to respond to said presence or absence of said kickback signal to provide an indication of a fault.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: November 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hiromichi Kuwano, Kaori Ichikawa
  • Publication number: 20020073379
    Abstract: An unsafe detection circuit for detecting a kickback signal including an input circuit for inputting a kickback signal, a circuit for detecting the presence or absence of said kickback signal, and a fault detection circuit to respond to said presence or absence of said kickback signal to provide an indication of a fault.
    Type: Application
    Filed: December 7, 2000
    Publication date: June 13, 2002
    Inventors: Hiromichi Kuwano, Kaori Ichikawa
  • Patent number: 6236524
    Abstract: An adjustable impedance boosting circuit comprises a differential pair of gain stage transistors. A magneto-resistive element may be coupled to the emitters of the gain stage transistors, and a collector load may be coupled to a collector of at least one of the gain stage transistors. The invention further comprises a variable impedance load coupled in parallel with at least a portion of the collector load, the variable impedance load operable to adjust the impedance of the boosting circuit in proportion to the resistance of the magneto-resistive element.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: May 22, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Bernard R. Gregoire, Hiromichi Kuwano
  • Patent number: 5930212
    Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to a predetermined position on an optical recording medium, includes a photo-detector and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: July 27, 1999
    Assignee: Fujitsu Limited
    Inventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
  • Patent number: 5909415
    Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to a predetermined position on an optical recording medium, e.g., magneto-optical disk. The control system includes a photo-detector constituted by at least two-divisional units, and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents. Preferably, the servo-error signal generating circuit includes at least one division circuit that has two pairs of transistors, two emitters in each pair of transistors being connected together into a common emitter, bias voltages of a direct current type being applied to the respective bases of transistors on one side, and the respective collectors of the transistors on one side being connected to a common connecting portion via resistors.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: June 1, 1999
    Assignee: Fujitsu Limited & Texas Instruments Japan
    Inventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
  • Patent number: 5812503
    Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam on a predetermined position on an optically recording medium includes a photo-detector constituted by at least two-divisional units and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between detection currents measured at the collectors of selected transistors in two pairs of transistors.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: September 22, 1998
    Assignee: Fujitsu Limited
    Inventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
  • Patent number: 5636191
    Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to predertermined position on an optically recording medium, e.g., magneto-optical disk, includes a photo-detector constituted by at least two-divisional units; and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: June 3, 1997
    Assignees: Fujitsu Limited, Texas Instruments Japan Limited
    Inventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
  • Patent number: 5566143
    Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to predetermined position on an optically recording medium, e,g., magneto-optical disk, includes a photo-detector constituted by at least two-divisional units; and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: October 15, 1996
    Assignee: Fujitsu Limited
    Inventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
  • Patent number: 5499028
    Abstract: An analog/digital converter providing a high conversion speed and resolution while greatly reducing the number of circuit elements. The A/D converter in a first embodiment is a 6-bit resolution flash A/D converter made up of a 3-bit lower A/D conversion section and a 3-bit upper A/D conversion section.
    Type: Grant
    Filed: December 9, 1993
    Date of Patent: March 12, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Hiromichi Kuwano, Hisashi Tahara
  • Patent number: 4954766
    Abstract: This invention relates to a power supply circuit wherein first transistors, resistors, ann sscood rajsitoos itt a polarity opposite to that of said first transistors are series-connected between the power supply side and the output side. In one embodiment, the circuit is provided as a semiconductor integrated circuit wherein first transistor elements, diffusion resistor elements, and second transistor elements with a polarity opposite to that of said first transistor elements are respectively formed on a common semiconductor substrate together with interconnects.
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: September 4, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Shuichi Ishikawa, Hiromichi Kuwano
  • Patent number: 4901132
    Abstract: A semiconductor device is primarily composed of a semiconductor substrate of a first conductivity type and a semidonductor layer of a second conductivity type formed in a principal plane of the semiconductor substrate. The device has both a bipolar transistor with the semiconductor layer itself being the collector region. The base region is of the first conductivity type and the emitter region is of the second conductivity type. Both regions are formed in the same layer as a JFET struture which includes the above collector region as channel a and the above base region as a gate. A semiconductor region of the first conductivity type is formed in the above semiconductor layer, the semiconductor layer itself, and the above base and emitter regions constitute a thyristor structure.
    Type: Grant
    Filed: January 31, 1989
    Date of Patent: February 13, 1990
    Assignee: Texas Instruments Incorporated
    Inventor: Hiromichi Kuwano
  • Patent number: 4857780
    Abstract: A high withstand voltage output circuit has a pull-up constant current source and transistor connected in series between the grounding side and supply voltage side wherein the breakdown voltage of the constant current source is set higher than the pinch-off voltage of the transistor.
    Type: Grant
    Filed: September 14, 1988
    Date of Patent: August 15, 1989
    Assignee: Texas Instrument Incorporated
    Inventor: Hiromichi Kuwano