Abstract: A delayed signal generation circuit includes a first delay circuit having a plurality of delay elements connected in series and delaying a reference signal applied thereto, a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit, a detector unit, responsive to the reference signal, for detecting a number of delay elements of the first delay circuit which output an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval, and a selection unit for selecting one delay element from the second delay circuit according to the number of delay elements of the first delay circuit, and for outputting the output signal from the selected delay element as a delayed signal.

Abstract: A microcomputer including a test-only RAM, a WDT (watchdog timer) and a clock controller. The test-only RAM stores information present on the address bus and data bus during the operation in a single-chip mode. The WDT counts a specified time interval according to a stored-ROM program in such a manner that it does not underflow. If the WDT underflows during the operation in the single-chip mode, it makes a decision that an abnormal event occurs, and outputs an underflow signal. The clock controller halts writing the address bus information and data bus information into the test-only RAM in response to the underflow signal. The microcomputer can easily identify an instruction which is being executed when a malfunction such as runaway occurs in the single-chip mode.

Abstract: A delayed signal generation circuit comprises a first delay circuit having a plurality of delay elements connected in series, the first delay circuit delaying a reference signal applied thereto, a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit, a detector unit, responsive to the reference signal applied to the first delay circuit, for detecting a number of delay elements of the first delay circuit which send out an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval, and a selection unit for selecting one delay element from among the plurality of delay elements of the second delay circuit according to the number of delay elements of the first delay circuit which is detected by the detector unit, and for sending out the output signal from the selected delay element of the second delay circuit as

Abstract: A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumulated so as to diverge the lag time, thereby speeding up the operation of the counter.