Abstract: Provided is an optical disk recording device including: a recording pulse information generation unit that generates, from a recording signal, recording pulse information corresponding to a power level of laser light; a recording code generation unit that generates a recording code by encoding the recording pulse information; and a decoded code generation unit that decodes the recording code. The recording code generation unit generates the recording code based on a cyclic cede representing each transmission of the power level by using a Gray code. The decoded code generation unit decodes the recording code by using a recording code corresponding to a power level at a predetermined timing and a recording code corresponding to a power level immediately prior to the power level at the predetermined timing.

Abstract: Provided is an optical disk recording device including: a recording pulse information generation unit that generates, from a recording signal, recording pulse information corresponding to a power level of laser light; a recording code generation unit that generates a recording code by encoding the recording pulse information; and a decoded code generation unit that decodes the recording code. The recording code generation unit generates the recording code based on a cyclic cede representing each transmission of the power level by using a Gray code. The decoded code generation unit decodes the recording code by using a recording code corresponding to a power level at a predetermined timing and a recording code corresponding to a power level immediately prior to the power level at the predetermined timing.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip having a delay unit and a delay time measuring unit for measuring a delay time. The delay time measuring unit generates a measurement result signal, which is a digital signal, based on the delay time, and outputs the measurement result signal outside the semiconductor chip.

Abstract: A fixed-length delay generation circuit comprises a first variable delay circuit (VDC), a clock generation circuit, a VDC group including one or more second VDCs, and a delay controller. The clock signal is input to a second VDC disposed at the initial stage in the VDC group. The delay controller outputs a signal by which delay amount in the first and second VDCs are made smaller when a difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is greater than a predetermined value. The delay controller outputs a signal by which delay amount in the first and second VDCs are made larger when the difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is smaller than such value.

Abstract: The PLL circuit in the disk drive, according to the present invention, is comprised of the following: a VCO (Voltage Controlled Oscillator) 11d, a frequency divider (DIV) 11e, a phase comparator (PC) 11a, a charge pump 11b, a low-pass filter (LPF) 11c, and a MIRR TE HOLD circuit 11f. Wherein, the LPF (Low-Pass Filter) 11c passes only low frequency components of the phase-error voltage, generated by the charge pump 11b, and provides the resulting, low frequency components passed, as a VCO control voltage, for the VCO. The phase comparator 11a compares the phase of a divided, VCO clock signal output from the frequency divider 11e, to that of an EFM signal. The divided, VCO clock signal results from the frequency-dividing of a VCO clock signal, which has been output from the VCO 11d, by the frequency divider 11e.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip having a delay unit and a delay time measuring unit for measuring a delay time. The delay time measuring unit generates a measurement result signal, which is a digital signal, based on the delay time, and outputs the measurement result signal outside the semiconductor chip.

Abstract: In a PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal, a mask circuit controls to transmit or block at least part or all of the phase error signal in accordance with the reference signal or the reproduction signal, an output different from the phase error signal from the phase comparator, and the signal to be compared.

Abstract: In a PLL circuit, a phase comparator compares phases between a data signal train and a regenerated clock generated within the PLL circuit based on a clock with which the data signal train is synchronizing, and outputs a phase error signal. A frequency comparator compares frequencies between the data stream signal and the regenerated clock and outputs a frequency error signal. When the frequency difference between the both is large, only the frequency system loop operates to carry out a frequency pull in operation of the regenerated clock. When the frequency difference becomes smaller than a predetermined value, an operation by the phase system loop is added to carry out a phase pull in operation. When the phase difference becomes a predetermined value, the phase is locked. When the frequency difference exceeds the predetermined value again during the phase locked period, the operation of the phase system loop is suspended and only the frequency system loop carries out the frequency pull in operation.

Abstract: A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a 1/117 frequency-divided signal as a frame period signal. A control unit counts the level transition interval of the EFM signal by the bit synchronizing clock signal, selects a maximum count value in a detecting duration defined by each frame period signal, and compares the maximum count value with a predetermined value corresponding to the bit length of a frame synchronizing signal included in the EFM signal.

Abstract: In a disk rotational velocity controlling circuit, an edge detection circuit 1 comprises a rising edge detector and a falling edge detector for detecting a rising edge and a falling edge of an EFM signal E, independently of each other.