Patents by Inventor Hiromichi Oribe

Hiromichi Oribe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8209465
    Abstract: Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 26, 2012
    Assignee: Hagiwara Sys-Com Co., Ltd.
    Inventors: Hiromichi Oribe, Masaki Takikawa, Yoshihiro Kitou
  • Publication number: 20090172267
    Abstract: A flash memory device includes a flash memory that stores many physical data blocks, a refresh management table that stores indications of the number of times each individual physical data block has been read, and a controller responsive to read and erase control signals from a source external to the flash memory device, and to the stored indications of the refresh management table for controlling reading, erasing and refreshing of the individual physical data blocks. In response to the number of times each individual physical data block has been read being equal to or exceeding a limit value, the controller refreshes the individual physical data block associated with the indication equaling or exceeding the limit value.
    Type: Application
    Filed: December 24, 2008
    Publication date: July 2, 2009
    Applicant: HAGIWARA SYS-COM CO., LTD.
    Inventors: Hiromichi ORIBE, Teruki ORIHASHI
  • Publication number: 20090113119
    Abstract: Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit.
    Type: Application
    Filed: October 30, 2008
    Publication date: April 30, 2009
    Applicant: HAGIWARA SYS-COM CO., LTD
    Inventors: Hiromichi ORIBE, Masaki Takikawa, Yoshihiro Kitou
  • Patent number: 7412558
    Abstract: Card-type memories have a memory unit with an area having a minimum memory capacity and a control unit for interpreting a command issued by a host system and controlling the memory unit in accordance with the command. The memory area is formatted in accordance with the universal disk format so each sector of the area has a user data area of 2048 bytes with a logical sector length of 2048 bytes. File management is performed by a UDF file system of a host computer.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: August 12, 2008
    Assignee: Hagiwara Sys-Com Co., Ltd.
    Inventors: Hiromichi Oribe, Yuji Oishi, Kimitoshi Nakamura
  • Publication number: 20060015676
    Abstract: Card-type memories have a memory unit with an area having a minimum memory capacity and a control unit for interpreting a command issued by a host system and controlling the memory unit in accordance with the command. The memory area is formatted in accordance with the universal disk format so each sector of the area has a user data area of 2048 bytes with a logical sector length of 2048 bytes. File management is performed by a UDF file system of a host computer.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 19, 2006
    Inventors: Hiromichi Oribe, Yuji Oishi, Kimitoshi Nakamura
  • Patent number: 6779067
    Abstract: An information storage device (10) includes a cartridge (14) removably inserted into a cradle (13) that has a drive module (18) releasably coupled to an interface module (17). A drive electronics circuit (71) in the drive module is coupled to a hard disk drive mechanism (56) in the cartridge, and is coupled through a bus switch (131) and a bus (122) to a bridge circuit (111) in the interface module. An auxiliary circuit (76) in the drive module is coupled to the bus, is controlled by the bridge circuit, operates the bus switch, and handles considerations relating to removability of the cartridge. The interface module is one of several interchangable interface modules which each have a different bridge circuit to interface the bus to a respective different communication protocol.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: August 17, 2004
    Assignee: Iomega Corporation
    Inventors: Todd R. Shelton, Theodore J. Smith, Marvin R. DeForest, Kelly D. Wright, Mark L. Reimann, Hiromichi Oribe, Jeffery D. Penman
  • Publication number: 20020169911
    Abstract: An information storage device (10) includes a cartridge (14) removably inserted into a cradle (13) that has a drive module (18) releasably coupled to an interface module (17). A drive electronics circuit (71) in the drive module is coupled to a hard disk drive mechanism (56) in the cartridge, and is coupled through a bus switch (131) and a bus (122) to a bridge circuit (111) in the interface module. An auxiliary circuit (76) in the drive module is coupled to the bus, is controlled by the bridge circuit, operates the bus switch, and handles considerations relating to removability of the cartridge. The interface module is one of several interchangable interface modules which each have a different bridge circuit to interface the bus to a respective different communication protocol.
    Type: Application
    Filed: May 14, 2001
    Publication date: November 14, 2002
    Inventors: Todd R. Shelton, Theodore J. Smith, Marvin R. DeForest, Kelly D. Wright, Mark L. Reimann, Hiromichi Oribe, Jeffery D. Penman