Patents by Inventor Hiromitsu Hirayama

Hiromitsu Hirayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5856917
    Abstract: Device including an input rectifying circuit 2 for effecting a full wave rectification on an AC input, and an output converter which includes a transforming device 11 having a primary winding 11a and a secondary winding 11b, the primary winding being connected through an inductor 16 with paired outputs of the input rectifying circuit, the secondary winding being connected through an output rectifying circuit with a load. Switching element 18 is controlled by a control circuit 20 to operate between ON and OFF states, and capacitor 19 is connected with the input rectifying circuit and the transforming device so as to be charged during the OFF state period of the switching element 18 through a charging circuit including the inductor 16, and to discharge during the ON state period through the primary winding 11a of the transforming device 11. The control circuit 20 controls the switching element to operate in an ON-OFF manner with a frequency faster than the frequency of the AC input.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: January 5, 1999
    Assignee: TDK Corporation
    Inventors: Kenichi Aonuma, Shigetaka Maeyama, Hiromitsu Hirayama, deceased, Hiroko Hirayama, heiress, Hiroshi Hirayama, heiress, Hisahiko Abe
  • Patent number: 5323071
    Abstract: A semiconductor integrated circuit device has an input logic level conversion circuit which receives an external input signal and some reference voltages, an internal logic circuit connected between a first and a second power supply terminal, which receives an output voltage from the input logic level conversion circuit and outputs an output signal at an output terminal, and a standard voltage generation circuit connected between the first and second power supply terminals, which has the same circuit configuration as that of the internal logic circuit and which outputs a standard voltage whose level is identical with the threshold value of the internal logic circuit. The standard voltage is supplied to the input logic level conversion circuit as one of the reference voltages. The standard voltage generation circuit is formed by at least a driver FET, a load element and a negative feedback resistor.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: June 21, 1994
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hirayama
  • Patent number: 5107144
    Abstract: An integrated circuit includes a logical part and a buffer part. A voltage clamping circuit is provided in parallel with a driver transistor of the logical part of the integrated circuit. The high level of the internal logical circuit is linked to the voltage of a first source power supply that is supplied to the driver transistor. A plurality of diodes may be used, connected in parallel as the voltage clamping circuit. A voltage clamping circuit may be formed alternatively by using a plurality of field transistors, each of the transistors using the gate as an anode and the short-circuited source and drain as a cathode, and the anode and the cathode are connected in series. An input buffer circuit of differential type configuration is used, and by inputting the voltage of a first source power supply to a reference voltage part of the input buffer circuit, the level conversion of an input voltage is made to be linked to variations of the voltage of the source power supply.
    Type: Grant
    Filed: March 2, 1990
    Date of Patent: April 21, 1992
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hirayama
  • Patent number: 5015873
    Abstract: A semiconductor integrated device for applying a switching signal and an offset signal in superposed relation to each other to an external load connectable between an output terminal and a power supply terminal, comprises an offset signal supplying circuit for supplying an offset signal to the output terminal and including a first field effect transistor having a drain electrode connected to the output terminal, and a second field effect transistor having substantially the same characteristics as the first field effect transistor. The second field effect transistor has a drain electrode connected to a source electrode of the first field effect transistor, a gate electrode connected to a control terminal receptive of a control signal effective to control the offset signal, and a source electrode connected to a negative power supply terminal.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: May 14, 1991
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hirayama
  • Patent number: 4939402
    Abstract: A single transistor type driving circuit for a piezoelectric vibrator. The driving circuit includes a transformer having a primary winding and a secondary winding, a single switching transistor connected in series with the primary winding, the piezoelectric vibrator being connected with the secondary winding, a transistor driving circuit for applying driving current to the switching transistor so that the switching transistor is alternately turned on and off to thereby drive the vibrator at or in the vicinity of a resonating frequency of the vibrator. A coil is connected in series with the piezoelectric vibrator so that current and voltage of sinusoidal form are applied to the vibrator. A phase comparator compares phase of the sinusoidal current at the piezoelectric vibrator with phase of voltage at the secondary winding of the transformer to produce a phase difference signal, and the frequency of the driving current is controlled in accordance with the phase difference signal.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: July 3, 1990
    Assignee: TDK Corporation
    Inventors: Hiromitsu Hirayama, Takashi Urano, Minoru Takahashi
  • Patent number: 4857975
    Abstract: A GaAs Schottky gate field effect transistor includes a GaAs substrate, source and drain electrodes ohmically attached to separated first and second parts of the GaAs substrate and a gate electrode of WSi contacted with a third part of the GaAs substrate between the first and second parts of the GaAs substrate, the gate electrode having a gate width of 30 to 60 .mu.m.
    Type: Grant
    Filed: August 14, 1987
    Date of Patent: August 15, 1989
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hirayama
  • Patent number: 4850534
    Abstract: A nebulizer which pumps up water and mists the pumped up water comprises an elongated main body with a center hole for water passage, and piezoelectric vibration elements together with electrodes for energizing the same mounted on the main body. The vibration elements are water-proofed, and the nebulizer itself is supported by using a flange on a water-proof member and the flange is on a plane on which a center electrode is positioned. Upon vibration of the elements, water is pumped up through the inlet of the main body, and is dissipated into the air through the outlet of the main body. Preferably, the inlet and the outlet are removable from the main body, and the inlet is coated with a thin hard film. Preferably, the outlet is covered with a mesh, or at least an opening of the outlet is covered for preventing the release of water that has not been convereted to mist.
    Type: Grant
    Filed: April 19, 1988
    Date of Patent: July 25, 1989
    Assignee: TDK Corporation
    Inventors: Minoru Takahashi, Kiyoto Sudou, Hiromitsu Hirayama
  • Patent number: 4743957
    Abstract: A gallium arsenide integrated circuit device compatible with a silicon emitter-coupled logic device includes a plurality of transistors constituting an logic circuit and an output transistor driving an externally provided load in response to an output of the logic circuit. The output transistor has its threshold voltage that is larger in absolute value than the threshold voltages of the remaining transistor, so that an output signal having the ECL level is produced without sacrificing a power consumption and a semiconductor chip area.
    Type: Grant
    Filed: May 2, 1986
    Date of Patent: May 10, 1988
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hirayama
  • Patent number: 4547705
    Abstract: Two fluorescent lamps are lightened by a single inverter circuit which provides switched power current to a single leakage transformer. The leakage transformer has a single primary winding coupled with said inverter circuit and a pair of secondary windings each coupled with a related fluorescent lamp. The core of said leakage transformer has a closed magnetic core with a pair of short legs each of which bridges across said closed magnetic path with a non-magnetic material so that said pair of short legs provides three windows and bypass leakage magnetic paths. The first window is defined by said pair of short legs, and each of the second and the third legs is defined by one of said short legs and said closed magnetic path. The primary winding is mounted in said first window, and each of said pair of secondary windings is mounted in said second or third window.
    Type: Grant
    Filed: January 27, 1983
    Date of Patent: October 15, 1985
    Assignee: TDK Corporation
    Inventors: Hiromitsu Hirayama, Hisashi Ebina
  • Patent number: 4327348
    Abstract: A variable leakage transformer or a variable voltage transformer comprising a magnetic core with a main-magnetic path and a sub-magnetic path, the main magnetic path having at least a common magnetic path with the submagnetic path, a primary winding wound on said common magnetic path of the core, a secondary winding wound on said main magnetic path of the core, means for controlling the magnetic flux in said sub-magnetic path, and said main-magnetic path having a thin air gap. By controlling the magnetic flux in the sub-magnetic path, the leakage of the flux induced by the primary winding from the main-magnetic path to the sub-magnetic path can be controlled. Thus the coupling between the primary and secondary windings, and conduction period in each cycle of the AC output voltage are controlled. The control of the conduction period in each cycle provides the control of the power transmitted from the primary winding to the secondary winding.
    Type: Grant
    Filed: October 3, 1979
    Date of Patent: April 27, 1982
    Assignee: TDK Electronics Co., Ltd.
    Inventor: Hiromitsu Hirayama