Patents by Inventor Hiromitsu IINO

Hiromitsu IINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262811
    Abstract: According to one embodiment, a semiconductor storage device includes a stacked section in which a plurality of conductor layers are stacked along a first direction and a stepped section in which the plurality of conductor layers are in a stepped shape. The stepped section includes a lower stepped section and an upper stepped section. In the upper stepped section, the conductor layers closer to the lower stepped section side along the first direction extend longer toward one side along a second direction orthogonal to the first direction. The lower stepped section is located at a position toward an opposite side to the one side along the second direction with respect to the upper stepped section.
    Type: Application
    Filed: August 5, 2021
    Publication date: August 18, 2022
    Inventors: Hiromitsu Iino, Shunpei Takeshita, Naoki Yamamoto, Kazuhiro Nojima
  • Patent number: 8791523
    Abstract: A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Iino, Tadashi Iguchi
  • Publication number: 20130234332
    Abstract: According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a plurality of contact electrodes, a plurality of first insulating portions, and a plurality of second insulating portions. The plurality of contact electrodes extends in a stacking direction of the stacked body. Each of the contact electrodes reaches corresponding one of the conductive layers. The plurality of first insulating portions respectively is provided between the plurality of contact electrodes and the stacked body. The plurality of second insulating portions respectively is provided between the plurality of first insulating portions and the stacked body.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu IINO, Tadashi IGUCHI
  • Patent number: 8530955
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Iino, Ryota Katsumata
  • Publication number: 20130056818
    Abstract: A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess.
    Type: Application
    Filed: March 16, 2012
    Publication date: March 7, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu IINO, Tadashi Iguchi
  • Publication number: 20120241843
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.
    Type: Application
    Filed: September 20, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHlKl KAISHA TOSHIBA
    Inventors: Hiromitsu IINO, Ryota KATSUMATA