Abstract: A method of processing a substrate includes loading the substrate on a substrate holder. The substrate includes a major surface and a feature disposed over the major surface. The feature has a first width along an etch direction. The method includes exposing portions of the major surface and changing the first width of the feature to a second width along the etch direction by etching a first portion of the sidewalls of the feature with a gas cluster ion beam oriented along a beam direction.

Abstract: A method of processing a substrate includes loading the substrate on a substrate holder. The substrate includes a major surface and a feature disposed over the major surface. The feature has a first width along an etch direction. The method includes exposing portions of the major surface and changing the first width of the feature to a second width along the etch direction by etching a first portion of the sidewalls of the feature with a gas cluster ion beam oriented along a beam direction.

Abstract: A method of processing a substrate includes loading the substrate on a substrate holder. The substrate includes a major surface and a feature disposed over the major surface. The feature has a first width along an etch direction. The method includes exposing portions of the major surface and changing the first width of the feature to a second width along the etch direction by etching a first portion of the sidewalls of the feature with a gas cluster ion beam oriented along a beam direction.

Abstract: A method of processing a substrate includes loading the substrate on a substrate holder. The substrate includes a major surface and a feature disposed over the major surface. The feature has a first width along an etch direction. The method includes exposing portions of the major surface and changing the first width of the feature to a second width along the etch direction by etching a first portion of the sidewalls of the feature with a gas cluster ion beam oriented along a beam direction.

Abstract: A method for etching a high-k dielectric layer on a substrate in a plasma processing system is described. The high-k dielectric layer can, for example, comprise HfO2. The method comprises elevating the temperature of the substrate above 200° C. (i.e., typically of order 400° C.), introducing a process gas comprising a halogen-containing gas, igniting a plasma from the process gas, and exposing the substrate to the plasma. The process gas can further include a reduction gas in order to improve the etch rate of HfO2 relative to Si and SiO2.

Abstract: A plasma processing system for treating a substrate includes a processing chamber including a first chamber portion configured to receive a first gas for providing a plasma space, and a second chamber portion configured to receive a second gas for providing a process space having process chemistry to treat the substrate. A substrate holder is coupled to the second chamber portion of the processing chamber, and configured to support the substrate proximate the process space, and a plasma source is coupled to the first chamber portion of the processing chamber, and configured to form a plasma in the plasma space. A grid is located between the plasma space and the process space, and configured to permit the diffusion of the plasma between the plasma space and the process space in order to form the process chemistry from the process gas.

Abstract: A plasma processing system for treating a substrate includes a processing chamber including a first chamber portion configured to receive a first gas for providing a plasma space, and a second chamber portion configured to receive a second gas for providing a process space having process chemistry to treat the substrate. A substrate holder is coupled to the second chamber portion of the processing chamber, and configured to support the substrate proximate the process space, and a plasma source is coupled to the first chamber portion of the processing chamber, and configured to form a plasma in the plasma space. A grid is located between the plasma space and the process space, and configured to permit the diffusion of the plasma between the plasma space and the process space in order to form the process chemistry from the process gas.

Abstract: A method and system for trimming a feature on a substrate is described. During a chemical treatment of the substrate, the substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. An inert gas is also introduced, and the flow rate of the inert gas is selected in order to affect a target trim amount during the trimming of the feature.

Abstract: A method for etching a high-k dielectric layer on a substrate in a plasma processing system is described. The high-k dielectric layer can, for example, comprise HfO2. The method comprises elevating the temperature of the substrate above 2000°C. (i.e., typically of order 400° C.), introducing a process gas comprising a halogen-containing gas, igniting a plasma from the process gas, and exposing the substrate to the plasma. The process gas can further include a reduction gas in order to improve the etch rate of HfO2 relative to Si and SiO2.

Abstract: A method for heating a substrate between a first process and a second process using a plasma is described. The heating method comprises thermally isolating the substrate on the substrate holder by removing the backside supply of a heat transfer gas and removing the clamping force. Furthermore, an inert gas, such as a Noble gas, is introduced to the plasma processing system and a plasma is ignited. The substrate is exposed to the inert plasma for a period of time sufficient to elevate the temperature of the substrate from a first temperature (i.e., typically less than 100° C.) to a second temperature (i.e., typically of order 400° C.).

Abstract: A method and processing tool are provided for trimming a gate electrode structure containing a gate electrode layer with a first dimension. A reaction layer is formed through reaction with the gate electrode structure. The reaction layer is the selectively removed from the unreacted portion of the gate electrode structure by chemical etching, thereby forming a trimmed gate electrode structure with a second dimension that is smaller than the first dimension. The trimming process can be carried out under process conditions where formation of the reaction layer is substantially self-limiting. The trimming process can be repeated to further reduce the dimension of the gate electrode structure.